參數(shù)資料
型號(hào): ML610Q412P-XXXWA
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類: 微控制器/微處理器
英文描述: RISC MICROCONTROLLER, UUC95
封裝: 2.83 MM X 2.63 MM, 0.35 MM HEIGHT, 0.80 MM PITCH, DIE-95
文件頁數(shù): 41/152頁
文件大?。?/td> 1641K
代理商: ML610Q412P-XXXWA
ML610Q411/ML610Q412/ML610Q415 User’s Manual
Chapter 10
Timers
10 – 8
10.2.6
Timer 0 Counter Register (TM0C)
Address: 0F031H
Access: R/W
Access size: 8 bits
Initial value: 00H
7
6
5
4
3
2
1
0
TM0C
T0C7
T0C6
T0C5
T0C4
T0C3
T0C2
T0C1
T0C0
R/W
Initial value
0
TM0C is a special function register (SFR) that functions as an 8-bit binary counter.
When write operation to TM0C is performed, TM0C is set to “00H”. The data that is written is meaningless.
In 16-bit timer mode and 16-bit timer frequency measurement mode, if write operation is performed to either the
low-order TM0C or high-order TM1C, both the low-order and the high-order are set to “0000H”.
During timer operation, the contents of TM0C may not be read depending on the conditions of the timer clock and the
system clock.
Table 10-1 shows whether a TM0C read is enabled or disabled during timer operation for each condition of the timer
clock and system clock.
Table 10-1
TM0C Read Enable/Disable during Timer Operation
Timer clock
T0CK
System clock
SYSCLK
TM0C read enable/disable
LSCLK
Read enabled
LSCLK
HSCLK
Read enabled. However, to prevent the reading of undefined data
during incremental counting, read TM0C twice and check that the
results match.
HTBCLK
LSCLK
Read disabled
HTBCLK
HSCLK
Read enabled
LSCLK
External clock
HSCLK
Read disabled
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