- 您現(xiàn)在的位置：買賣IC網 > PDF目錄69034 > ML60851EGA (LAPIS SEMICONDUCTOR CO LTD) UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 PDF資料下載
參數資料
| 型號： | ML60851EGA |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封裝： | 0.80 MM PITCH, PLASTIC, QFP-44 |
| 文件頁數： | 64/85頁 |
| 文件大小： | 387K |
| 代理商： | ML60851EGA |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁當前第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁
FEDL60851E-01
OKI Semiconductor
ML60851E
66/84
Interrupts
The ML60851E requests interrupts to the local MCU, etc., by asserting the -INTR pin. The interrupt causes are the
following:
(a)
Setup ready for the 8-byte setup data
(b)
EP0 receive packet ready
(c)
EP0 transmit packet ready
(d)
EP1 transmit/receive packet ready
(e)
EP2 transmit/receive packet ready
(f)
EP3 transmit packet ready
(g)
USB Bus reset
(h)
Suspend
Although there is only one
INTR pin, the local MCU can identify the contents of the interrupt by reading out the
interrupt status register. These interrupts can also be masked dynamically by making individual settings in the
interrupt enable register.
The causes of the interrupts, their setting and resetting conditions, and the responses to them are described below.
The functions of the setup ready bit and the packet ready bit can, in some situations, be different from those
described here because of some special automatic operations done by the ML60851E. Please see the descriptions
of the registers EP0STAT and PKTRDY for more details of such functions.
(1) Setup ready interrupt
Operation
Source of operation
Description (conditions, responses, etc.)
Setup ready
interrupt generation
ML60851E
The setup ready bit (D0 of EP0STAT) is asserted when the
8-byte setup control data is received normally and has
been stored in the set of setup registers.
An interrupt is generated at this time if D0 of INTENBL has
been asserted.
→ The firmware can now read the set of setup registers.
End of setup ready interrupt Local MCU (firmware)
After making the firmware read the 8-byte setup data, write
a “1” in bit D0 of EP0 status register (EP0STAT). This
causes the interrupt to be de-asserted.
The interrupt will not be de-asserted If a new 8-byte setup
data is received during this period. In this case, discard the
setup data that was being read at that time and read the
new 8-byte setup data.
The following table outlines the relationship between ML60851E registers and setup ready interrupt generation.
INTENBL(D0)
EP0STAT(D0)
INTSTAT(D0)
1
0
1
0
X
0
X This symbol means that it does not matter whether the value is ‘1’ or ‘0’
相關PDF資料 |
PDF描述 |
|---|---|
| ML60851EGA | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| ML60851ETB | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| ML610Q346 | RISC MICROCONTROLLER, PQFP64 |
| ML610346 | RISC MICROCONTROLLER, PQFP64 |
| ML610Q347J-NNNTB | 8-BIT, FLASH, 4.2 MHz, RISC MICROCONTROLLER, PQFP64 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ML60851ETB | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:USB Device Controller |
| ML60852 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:USB Device Controller |
| ML60852A | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:USB Device Controller |
| ML60852ATBZ010 | 功能描述:USB 接口集成電路 12 Mbps; USB Device Controller RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ML60852ATBZ03A | 制造商:ROHM Semiconductor 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。