參數(shù)資料
型號: ML60851EGA
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封裝: 0.80 MM PITCH, PLASTIC, QFP-44
文件頁數(shù): 15/85頁
文件大小: 387K
代理商: ML60851EGA
FEDL60851E-01
OKI Semiconductor
ML60851E
21/84
Revision Register (REVISION)
Read address
CDh
Write address
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
After a bus reset
Definition
Revision No. of Chip
Transmit FIFO Clear Register (CLRFIFO)
Read address
Write address
4Eh
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
Cannot be read (indeterminate)
After a bus reset
Cannot be read (indeterminate)
Definition
0
EP1 to EP3 FIFO Clear:
When each EP has been set for transmission, by writing a “1” in these bits, the
corresponding FIFOs are cleared at the Write pulse and also the corresponding EP
Packet Ready bits are reset.
EP1 Transmit FIFO Clear
EP2 Transmit FIFO Clear
EP3 Transmit FIFO Clear
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