參數(shù)資料
型號: ML60851EGA
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封裝: 0.80 MM PITCH, PLASTIC, QFP-44
文件頁數(shù): 62/85頁
文件大小: 387K
代理商: ML60851EGA
FEDL60851E-01
OKI Semiconductor
ML60851E
64/84
FIFO Control
The FIFO Control block controls all FIFO operations for transmitting and receiving USB packets.
The FIFO configuration is described below.
Endpoint FIFO/8-Byte Setup Register Configuration
FIFO type
Endpoint address
Program size
Function
Reception
0
8 Bytes
Transfer control
Transmission
0
8 Bytes
Transfer control
Reception/Transmission
1
64 Bytes (2 levels)
Bulk-In and bulk-Out
Reception/Transmission
2
64 Bytes
Bulk-Out and bulk-In
Transmission
3
8 Bytes
Interrupt
Every FIFO has a flag that indicates a full or empty FIFO and the capability of re-transmitting and re-receiving
data. Endpoint addresses 1 and 2 can be used for either of reception and transmission by writing the register.
The FIFO at endpoint address 1 can be used for DMA transfer.
8-Byte
Setup Register
Setup Ready
Endpoint Address 0
8-Byte
FIFO Rx
EP0 Receive FIFO
Packet Ready
Endpoint Address 0
8-Byte
FIFO Tx
EP0 Transmit FIFO
Packet Ready
Endpoint Address 0
Endpoint Address 1
64-Byte
FIFO
EP2 FIFO (64 bytes)
(Selectable for transmitter
or receiver)
EP1 FIFO (128 bytes)
(Selectable for transmitter
or receiver)
Packet Ready
Endpoint Address 2
64-Byte
FIFO
8-Byte
FIFO
EP3 FIFO (8 bytes)
Packet Ready
Endpoint Address 3
64-Byte
FIFO
Packet Ready
For Bulk Transfer
DMA Request
For Control Transfer
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