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參數(shù)資料
| 型號(hào)： | ML60851EGA |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封裝： | 0.80 MM PITCH, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 6/85頁 |
| 文件大?。?/td> | 387K |
| 代理商： | ML60851EGA |
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FEDL60851E-01
OKI Semiconductor
ML60851E
13/84
Packet Error Register (PKTERR)
Read address
C2h
Write address
—
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
After a bus reset
0
Definition
0
Each bit is asserted when the corresponding error occurs and is deasserted when SOP is received.
This register is used to report the error information. This register is useful for the tests during development, or for
preparing the error frequency measurement report. This register is not required by USB Specifications.
FIFO Status Register 1 (FIFOSTAT1)
Read address
C3h
Write address
—
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
1
0
1
0
After a bus reset
0
1
0
1
0
Definition
0
This register reports the status of EP0RXFIFO and the FIFO for EP1. Normally, there is no need to read this
register because it is sufficient to read the packet ready status before reading out or writing in a FIFO.
Receive FIFO0 Full:
This bit becomes “1” when 8-bytes of data are stored in the EP0RXFIFO. This bit is
not set to “1” when a packet less than 8 bytes long (a short packet) is stored in.
Receive FIFO0 Empty: This bit will be “1” when EP0RXFIFO is empty.
FIFO1 Full:
This bit becomes “1” when 64 bytes of data is stored in the FIFO for EP1. This is true
during both transmission and reception. This bit does not become “1” in the case of a
short packet. The FIFO for EP1 has a two-layer structure and can store up to 128
bytes of data. This bit indicates the status of the FIFO in which data is being written at
that time. In other words, this bit indicates the status of the FIFO into which the host
computer is writing data when EP1 is receiving data, and of the FIFO into which the
local MCU is writing data when EP1 is transmitting data.
FIFO1 Empty:
This bit becomes “1” when the FIFO for EP1 is empty. This is true during both
transmission and reception. The FIFO for EP1 has a two-layer structure and can store
up to 128 bytes of data. This bit indicates the status of the FIFO which is being read
out at that time.
Bit stuff error (R)
Data CRC error (R)
Address CRC error (R)
PID Error (R)
Receive FIFO0 Full (R)
Receive FIFO0 Empty (R)
FIFO1 Full (R)
FIFO1 Empty (R)
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| ML60851EGA | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
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| ML610Q346 | RISC MICROCONTROLLER, PQFP64 |
| ML610346 | RISC MICROCONTROLLER, PQFP64 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ML60851ETB | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:USB Device Controller |
| ML60852 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:USB Device Controller |
| ML60852A | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:USB Device Controller |
| ML60852ATBZ010 | 功能描述:USB 接口集成電路 12 Mbps; USB Device Controller RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ML60852ATBZ03A | 制造商:ROHM Semiconductor 功能描述: |
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