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參數(shù)資料
| 型號： | MK20X512VMD100R |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC MICROCONTROLLER, PBGA144 |
| 封裝： | 13 X 13 MM, MAPBGA-144 |
| 文件頁數(shù)： | 9/67頁 |
| 文件大?。?/td> | 997K |
| 代理商： | MK20X512VMD100R |
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6. 2 MHz core, system, bus and FlexBus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral
clocks enabled but peripherals are not in active operation. Code executing from flash.
7. 2 MHz core, system, bus and FlexBus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral
clocks disabled.
5.1.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
All peripheral clocks disabled except FTFL
LVD disabled, USB regulator disabled
No GPIOs toggled
Code execution from flash
Figure 1. Run mode supply current vs. core frequency — all peripheral clocks disabled
The following data was measured under these conditions:
MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
All peripheral clocks enabled but peripherals are not in active operation
LVD disabled, USB regulator disabled
General
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
17
Preliminary
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