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參數(shù)資料
| 型號： | MK20X512VMD100R |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC MICROCONTROLLER, PBGA144 |
| 封裝： | 13 X 13 MM, MAPBGA-144 |
| 文件頁數(shù)： | 18/67頁 |
| 文件大?。?/td> | 997K |
| 代理商： | MK20X512VMD100R |
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Table 12. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
tirefstf
Internal reference startup time (fast clock)
—
TBD
s
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
kHz
FLL
fdco_t
DCO output fre‐
quency range —
user trimmed
and DMX32=0
Low range (DRS=00)
640 × fints_t
20
20.97
25
MHz
Mid range (DRS=01)
1280 × fints_t
40
41.94
50
MHz
Mid-high range (DRS=10
192)0 × fints_t
60
62.91
75
MHz
High range (DRS=11)
2560 × fints_t
80
83.89
100
MHz
fdco_t_DMX3
2
DCO output fre‐
quency range —
reference =
32,768Hz and
DMX32=1
Low range (DRS=00)
732 × fints_t
—
23.99
—
MHz
Mid range (DRS=01)
1464 × fints_t
—
47.97
—
MHz
Mid-high range (DRS=10)
2197 × fints_t
—
71.99
—
MHz
High range (DRS=11)
2929 × fints_t
—
95.98
—
MHz
Jcyc_fll
FLL period jitter
—
TBD
ps
Jacc_fll
FLL accumulated jitter of DCO output over a 1s
time window
—
TBD
ps
tfll_acquire FLL target frequency acquisition time
—
1
ms
PLL
fvco
VCO operating frequency
48.0
—
100
MHz
fpll_ref
PLL reference frequency range
2.0
—
4.0
MHz
Jcyc_pll
PLL period jitter
—
400
—
ps
Jacc_pll
PLL accumulated jitter over 1s window
—
TBD
—
ps
Dlock
Lock entry frequency tolerance
± 1.49
—
± 2.98
%
Dunl
Lock exit frequency tolerance
± 4.47
—
± 5.97
%
tpll_lock
Lock detector detection time
—
0.15 +
1075(1/
fpll_ref)
ms
1. The resulting system clock frequencies should not exceed their maximum specified values.
Peripheral operating requirements and behaviors
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
25
Preliminary
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