參數(shù)資料
型號: MK20X512VMD100R
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: RISC MICROCONTROLLER, PBGA144
封裝: 13 X 13 MM, MAPBGA-144
文件頁數(shù): 29/67頁
文件大?。?/td> 997K
代理商: MK20X512VMD100R
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
Table 22. Flexbus switching specifications
Num
Description
Min.
Max.
Unit
Notes
Operating voltage
2.7
3.6
V
Frequency of operation
50
Mhz
FB1
Clock period
20
ns
FB2
Address, data, and control output valid
TBD
11.5
ns
FB3
Address, data, and control output hold
0
ns
FB4
Data and FB_TA input setup
8.5
ns
FB5
Data and FB_TA input hold
0.5
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Address
Data
TSIZ
AA=1
AA=0
AA=1
AA=0
FB1
FB3
FB5
FB4
FB5
FB2
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB_CSn
FB_OEn
FB_BE/BWEn
FB_TA
FB_TSIZ[1:0]
Figure 11. FlexBus read timing diagram
Peripheral operating requirements and behaviors
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
35
Preliminary
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