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型號(hào)：	MD80C32U-30:D
廠商：	ATMEL CORP
元件分類(lèi)：	微控制器/微處理器
英文描述：	MICROCONTROLLER
文件頁(yè)數(shù)：	951/1262頁(yè)
文件大?。?/td>	3503K

11028E–ATARM–22-Apr-13

–Enable Channel x, writing one to DMAC_CHER[x]. The DMAC is ready and

waiting for request.

Wait for XFRDONE in HSMCI_SR register.

Block Length is Not Multiple of 4 and Padding Not Used (ROPT field in HSMCI_DMA register set to 0)

In the previous DMA transfer flow (block length multiple of 4), the DMA controller is configured to

use only WORD AHB access. When the block length is no longer a multiple of 4 this is no longer

true. The DMA controller is programmed to copy exactly the block length number of bytes using

2 transfer descriptors.

Use the previous step until READ_SINGLE_BLOCK then

Program the DMA controller to use a two descriptors linked list.

Read the channel Register to choose an available (disabled) channel.

Clear any pending interrupts on the channel from the previous DMA transfer by

reading the DMAC_EBCISR register.

Program the channel registers in the Memory for the first descriptor. This descriptor

will be word oriented. This descriptor is referred to as LLI_W, standing for LLI word

oriented transfer.

The LLI_W.DMAC_SADDRx field in memory must be set with the starting address

of the HSMCI_FIFO address.

The LLI_W.DMAC_DADDRx field in the memory must be word aligned.

Program LLI_W.DMAC_CTRLAx with the following field’s values:

–DST_WIDTH is set to WORD.

–SRC_WIDTH is set to WORD.

–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.

–BTSIZE is programmed with block_length/4. If BTSIZE is zero, this descriptor is

skipped later.

Program LLI_W.DMAC_CTRLBx with the following field’s values:

–DST_INCR is set to INCR

–SRC_INCR is set to INCR

–FC field is programmed with peripheral to memory flow control mode.

–SRC_DSCR is set to zero. (descriptor fetch is enabled for the SRC)

–DST_DSCR is set to one. (descriptor fetch is disabled for the DST)

–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, DMA

controller is able to prefetch data and write HSMCI simultaneously.

Program LLI_W.DMAC_CFGx register for channel x with the following field’s

–FIFOCFG defines the watermark of the DMA channel FIFO.

–DST_REP is set to zero meaning that address are contiguous.

–SRC_H2SEL is set to true to enable hardware handshaking on the destination.

–SRC_PER is programmed with the hardware handshaking ID of the targeted

HSMCI Host Controller.

Program LLI_W.DMAC_DSCRx with the address of LLI_B descriptor. And set

DSCRx_IF to the AHB Layer ID. This operation actually links the Word oriented

相關(guān)PDF資料	PDF描述
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IR80C52XXX-30SHXXX:RD	8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQCC44
MC80C32E-36/883:D	8-BIT, 36 MHz, MICROCONTROLLER, CDIP40

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
MD80C51	制造商:TEMIC 制造商全稱(chēng):TEMIC Semiconductors 功能描述:CMOS 0 to 44 MHz Single-Chip 8 Bit Microcontroller
MD80C51BH	制造商:ROCHESTER 制造商全稱(chēng):ROCHESTER 功能描述:CMOS SINGLE - CHIP 8-BIT MICROCOMPUTER 64K program Memory Space
MD80C51FB	制造商:Rochester Electronics LLC 功能描述:
MD80C86	制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor
MD80C862	制造商:Intel 功能描述:PROCESSOR:MICRO-PROCESSOR

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