1128
11028E–ATARM–22-Apr-13
SAM9G46
47.4.2
Processing Period
The processing period can be configured.
The short processing period allows to allocate bandwidth to the SHA module whereas the long
processing period allocates more bandwidth to other applications (example: PDC).
In SHA1 mode, the short processing period is 85 clock cycles + 2 clock cycles for start command
synchronization. The long period is 326 clock cycles + 2 clock cycles.
In SHA256 mode, the short processing period is 72 clock cycles + 2 clock cycles for start com-
mand synchronization. The long period is 265 clock cycles + 2 clock cycles.
47.4.3
Start Modes
The SMOD field in the SHA Mode Register (SHA_MR) is used to select the hash processing
start mode.
47.4.3.1
Manual Mode
The sequence is as follows:
Set the bit DATRDY (Data Ready) in the SHA Interrupt Enable Register (SHA_IER),
depending on whether an interrupt is required or not at the end of processing.
For the first 512-bit block of a message, the FIRST command must be set by writing a 1 into
the corresponding bit of the Control Register (SHA_CR). For the other blocks, there is
nothing to write in this Control Register.
Write the 512-bit block to be processed in the Input Data Registers.
Set the START bit in the SHA Control Register SHA_CR to begin the processing.
When the processing completes, the bit DATRDY in the SHA Interrupt Status Register
(SHA_ISR) raises. If an interrupt has been enabled by setting the bit DATRDY in SHA_IER,
the interrupt line of the SHA is activated.
Repeat the write procedure for each 512-bit block, start procedure and wait for the interrupt
procedure up to the last 512-bit block of the entire message. Each time the start procedure is
complete, the DATRDY flag is cleared.
After the last block is processed (DATRDY flag is set, if an interrupt has been enabled by
setting the bit DATRDY in SHA_IER, the interrupt line of the SHA is activated), read the
message digest in the Output Data Registers. The DATRDY flag is automatically cleared
when reading the SHA_ODATAxR read only registers.
47.4.3.2
Auto Mode
Auto Mode is similar to Manual Mode, except that in this mode, as soon as the correct number of
Input Data Registers is written, processing is automatically started without any action in the con-
trol register.
47.4.3.3
PDC Mode
The Peripheral Data Controller (PDC or Peripheral DMA) can be used in association with the
SHA to perform the algorithm on a complete message without any action by the software during
processing.
In this starting mode, the type of the data transfer is set in words:
The sequence is as follows: