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11028E–ATARM–22-Apr-13

transfer. Only DMAC_CTRLAx register is written out, because only the

DMAC_CTRLAx.BTSIZE and DMAC_CTRLAx.DONE fields have been updated by

hardware within the DMAC. The LLI.DMAC_CTRLAx.DONE bit is asserted to indicate

buffer completion Therefore, software can poll the LLI.DMAC_CTRLAx.DONE field of

the DMAC_CTRLAx register in the LLi to ascertain when a buffer transfer has

Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead poll the

LLI.DMAC_CTRLAx.DONE bit in the LLI for that buffer. If the polled LLI.DMAC_CTRLAx.DONE bit

is asserted, then this buffer transfer has completed. This LLI.DMAC_CTRLA.DONE bit was

cleared at the start of the transfer.

18. The DMAC reloads the DMAC_SADDRx register from the initial value. Hardware sets

the buffer complete interrupt. The DMAC samples the row number as shown in Table

42-2 on page 978. If the DMAC is in Row 1, then the DMAC transfer has completed.

Hardware sets the transfer complete interrupt and disables the channel. You can either

respond to the Buffer Complete or Chained buffer Transfer Complete interrupts, or poll

for the Channel Enable (DMAC_CHSR.ENABLE) bit until it is cleared by hardware, to

detect when the transfer is complete. If the DMAC is not in Row 1 as shown in Table 42-

2 on page 978, the following step is performed.

19. The DMAC fetches the next LLI from memory location pointed to by the current

DMAC_DSCRx register, and automatically reprograms the DMAC_DADDRx,

DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx channel registers. Note that the

DMAC_SADDRx is not re-programmed as the reloaded value is used for the next

DMAC buffer transfer. If the next buffer is the last buffer of the DMAC transfer then the

DMAC_CTRLBx and DMAC_DSCRx registers just fetched from the LLI should match

Row1of Table 42-2 on page 978. The DMAC transfer might look like that shown in Fig-

Figure 42-11. Multi-buffer DMAC Transfer with Source Address Auto-reloaded and Linked List Destination Address

Source Layer

Destination Layer

Source Buffers

Destination Buffers

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