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11028E–ATARM–22-Apr-13

No UDP HS, UHP FS and DDR2 Mode

Only PLLA is running at 384 MHz, UPLL power consumption is saved

USB Device High Speed and Host EHCI High Speed operations are NOT allowed

Full Speed OHCI input clock is PLLACK, USBDIV is 7 (division by 8)

System Input clock is PLLACK, PCK is 384 MHz

MDIV is ‘11’, MCK is 128 MHz

DDR2 can be used at up to 128 MHz

Master Clock Controller

The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is

the clock provided to all the peripherals and the memory controller.

The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting

the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock

saves power consumption of the PLLA.

The Master Clock Controller is made up of a clock selector and a prescaler. It also contains a

Master Clock divider which allows the processor clock to be faster than the Master Clock.

The Master Clock selection is made by writing the CSS field (Clock Source Selection) in

PMC_MCKR (Master Clock Register). The prescaler supports the division by a power of 2 of the

selected clock between 1 and 64. The PRES field in PMC_MCKR programs the prescaler. The

Master Clock divider can be programmed through the MDIV field in PMC_MCKR.

It is forbidden to modify MDIV and CSS at the same access. Each field must be modified sepa-

rately with a wait for MCKRDY flag between the first field modification and the second field

modification.

Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in

PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can

trigger an interrupt to the processor. This feature is useful when switching from a high-speed

clock to a lower one to inform the software when the change is actually done.

Figure 26-2. Master Clock Controller

Processor Clock Controller

The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle

Mode. The Processor Clock can be disabled by writing the System Clock Disable Register

Master Clock

To the Processor

Clock Controller (PCK)

相關(guān)PDF資料	PDF描述
MC80C52XXX-20/883	8-BIT, MROM, 20 MHz, MICROCONTROLLER, CDIP40
IC80C52CXXX-36D	8-BIT, MROM, 36 MHz, MICROCONTROLLER, CDIP40
IT80C52CXXX-L16:RD	8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44
IR80C52XXX-30SHXXX:RD	8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQCC44
MC80C32E-36/883:D	8-BIT, 36 MHz, MICROCONTROLLER, CDIP40

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
MD80C51	制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 44 MHz Single-Chip 8 Bit Microcontroller
MD80C51BH	制造商:ROCHESTER 制造商全稱:ROCHESTER 功能描述:CMOS SINGLE - CHIP 8-BIT MICROCOMPUTER 64K program Memory Space
MD80C51FB	制造商:Rochester Electronics LLC 功能描述:
MD80C86	制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor
MD80C862	制造商:Intel 功能描述:PROCESSOR:MICRO-PROCESSOR

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