1238
11028E–ATARM–22-Apr-13
SAM9G46
52.2
SAM9G46 Errata - Rev. A Parts
52.2.1
Boot ROM
52.2.1.1
Boot ROM: NAND Flash boot does not support ECC Correction
The boot ROM allows booting from block 0 of a NAND Flash connected on CS3. However, the
boot ROM does not feature ECC correction on a NAND Flash.
Most of the NAND Flash vendors do not guarantee anymore that block 0 is error free. Therefore
we advise to locate the bootstrap program into another device supported by the boot ROM
(DataFlash, Serial Flash, SDCARD or EEPROM), and to implement a NAND Flash access with
ECC.
Problem Fix/Workaround
None.
52.2.1.2
Boot ROM: Boot issue on AT45-series SPI dataflash
The boot from AT45-series SPI DataFlash is not functional except for the AT45DB321D. Future
revisions of the AT45DB321D might not be functional either.
Problem Fix/Workaround
Use AT25-series Serial Flash instead.
52.2.2
RSTC
52.2.2.1
RSTC: Software reset during DDRAM accesses
When a software reset (CPU and peripherals) occurs during DDRAM read access, the CPU will
stop the DDRAM clock.
The DDRAM maintains the data on the bus until the clock restarts. This will create a bus conflict
if another memory sharing the external bus with the DDRAM is accessed prior to completion of
the read access to the DDRAM. Such a conflict will occur when the device boots out of an exter-
nal NAND or NOR Flash following the software reset.
Problem Fix/Workaround
1.
Boot from serial Flash
2.
Before generating the software reset, the user must ensure that all the accesses to
DDRAM are completed and then put the DDRAM in self-refresh mode. The routine to
generate the software reset must be located in internal SRAM or in the ARM cache
memory.
52.2.3
Error Corrected Code Controller (ECC)
52.2.3.1
ECC: Computation with a 1 clock cycle long NRD/NWE pulse
If the SMC is programmed with NRD/NWE pulse length equal to 1 clock cycle, ECC cannot com-
pute the parity.
Problem Fix/Workaround
It is recommended to program SMC with a value superior to 1.