參數(shù)資料
型號: MCIMX357DVM5BR2
廠商: Freescale Semiconductor
文件頁數(shù): 99/147頁
文件大?。?/td> 0K
描述: IC MPU I.MX35 400MAPBGA
標(biāo)準(zhǔn)包裝: 1,000
系列: i.MX35
核心處理器: ARM11
芯體尺寸: 32-位
速度: 532MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),I²C,MMC,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 96
程序存儲器類型: ROMless
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.33 V ~ 1.47 V
振蕩器型: 外部
工作溫度: -20°C ~ 70°C
封裝/外殼: 400-LFBGA
包裝: 帶卷 (TR)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
55
NOTE
SDRAM CLK and DQS-related parameters are measured from the 50%
point—that is, “high” is defined as 50% of signal value and “l(fā)ow” is defined
as 50% of signal value.
The timing parameters are similar to the ones used in SDRAM data sheets.
Table 44 indicates SDRAM requirements. All output signals are driven by
the ESDCTL at the negative edge of SDCLK, and the parameters are
measured at maximum memory frequency.
Figure 35. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram
NOTE
SDRAM CLK and DQS-related parameters are measured from the 50%
point—that is, “high” is defined as 50% of signal value, and “l(fā)ow” is defined
as 50% of signal value.
The timing parameters are similar to the ones used in SDRAM data sheets.
Table 45 indicates SDRAM requirements. All output signals are driven by
the ESDCTL at the negative edge of SDCLK, and the parameters are
measured at maximum memory frequency.
Table 45. Mobile DDR SDRAM Read Cycle Timing Parameters
ID
Parameter
Symbol
Min. Max. Unit
SD21 DQS – DQ Skew (defines the Data valid window in read cycles related to DQS).
tDQSQ
0.85
ns
SD22 DQS DQ HOLD time from DQS
tQH
2.3
ns
SD23 DQS output access time from SDCLK posedge
tDQSCK
6.7
ns
SDCLK
DQS (input)
DQ (input)
Data
SD23
SD21
SD22
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