參數(shù)資料
型號： MCIMX357DVM5BR2
廠商： Freescale Semiconductor
文件頁數(shù)： 77/147頁
文件大小： 0K
描述： IC MPU I.MX35 400MAPBGA
標準包裝： 1,000
系列： i.MX35
核心處理器： ARM11
芯體尺寸： 32-位
速度： 532MHz
連通性： 1 線，CAN，EBI/EMI，以太網(wǎng)，I²C，MMC，SPI，SSI，UART/USART，USB OTG
外圍設備： DMA，I²S，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 96
程序存儲器類型： ROMless
RAM 容量： 128K x 8
電壓 - 電源 (Vcc/Vdd)： 1.33 V ~ 1.47 V
振蕩器型： 外部
工作溫度： -20°C ~ 70°C
封裝/外殼： 400-LFBGA
包裝： 帶卷 (TR)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
35
NOTE
High is defined as 80% of signal value and low is defined as 20% of signal
value.
Timing for HCLK is 133 MHz and internal NFC clock (flash clock) is
approximately 33 MHz (30 ns). All timings are listed according to this NFC
clock frequency (multiples of NFC clock phases), except NF16 and NF17,
which are not NFC clock related.
4.9.5.2
Wireless External Interface Module (WEIM)
All WEIM output control signals may be asserted and deasserted by internal clocks related to the BCLK
rising edge or falling edge according to the corresponding assertion or negation control fields. The address
always begins related to BCLK falling edge but may be ended both on rising and falling edge in muxed
mode according to control register configuration. Output data begins related to BCLK rising edge except
in muxed mode where both rising and falling edge may be used according to control register configuration.
NF5
NF_WP pulse width
tWP
T – 1.0 ns
29
ns
NF6
NFALE setup time
tALS
T – 4.0 ns
—
26
—
ns
NF7
NFALE hold time
tALH
T – 4.5 ns
—
25.5
—
ns
NF8
Data setup time
tDS
T – 2.0 ns
—
28
—
ns
NF9
Data hold time
tDH
T – 5.0 ns
—
25
—
ns
NF10
Write cycle time
tWC
2T – 3.0 ns
57
ns
NF11
NFWE hold time
tWH
T – 5.0 ns
25
ns
NF12
Ready to NFRE low
tRR
6T
—
180
—
ns
NF13
NFRE pulse width
tRP
1.5T – 1.0 ns
—
44
—
ns
NF14
READ cycle time
tRC
2T – 5.5 ns
—
54.5
—
ns
NF15
NFRE high hold time
tREH
0.5T – 4.0 ns
11
—
ns
NF16
Data setup on READ
tDSR
N/A
9
—
ns
NF17
Data hold on READ
tDHR
N/A
0
—
ns
1 The flash clock maximum frequency is 50 MHz.
2 Subject to DPLL jitter specification listed in Table 28, "DPLL Specifications," on page 31.
Table 32. NFC Timing Parameters1 (continued)
ID
Parameter
Symbol
Timing
T = NFC Clock Cycle2
Example Timing for
NFC Clock
≈ 33 MHz
T = 30 ns
Unit
Min.
Max.
Min.
Max.
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