參數(shù)資料
型號： MCIMX357DVM5BR2
廠商： Freescale Semiconductor
文件頁數(shù)： 101/147頁
文件大?。?/td> 0K
描述： IC MPU I.MX35 400MAPBGA
標(biāo)準(zhǔn)包裝： 1,000
系列： i.MX35
核心處理器： ARM11
芯體尺寸： 32-位
速度： 532MHz
連通性： 1 線，CAN，EBI/EMI，以太網(wǎng)，I²C，MMC，SPI，SSI，UART/USART，USB OTG
外圍設(shè)備： DMA，I²S，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 96
程序存儲器類型： ROMless
RAM 容量： 128K x 8
電壓 - 電源 (Vcc/Vdd)： 1.33 V ~ 1.47 V
振蕩器型： 外部
工作溫度： -20°C ~ 70°C
封裝/外殼： 400-LFBGA
包裝： 帶卷 (TR)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 10
Freescale Semiconductor
57
80
SCKT rising edge to FST out (wr) high5
—
20.0
10.0
x ck
i ck
ns
81
SCKT rising edge to FST out (wr) low5
—
22.0
12.0
x ck
i ck
ns
82
SCKT rising edge to FST out (wl) high
—
19.0
9.0
x ck
i ck
ns
83
SCKT rising edge to FST out (wl) low
—
20.0
10.0
x ck
i ck
ns
84
SCKT rising edge to data out enable from high
impedance
—
22.0
17.0
x ck
i ck
ns
86
SCKT rising edge to data out valid
—
18.0
13.0
x ck
i ck
ns
87
SCKT rising edge to data out high impedance 67
—
21.0
16.0
x ck
i ck
ns
89
FST input (bl, wr) setup time before SCKT falling edge5
—
2.0
18.0
—
x ck
i ck
ns
90
FST input (wl) setup time before SCKT falling edge
—
2.0
18.0
—
x ck
i ck
ns
91
FST input hold time after SCKT falling edge
—
4.0
5.0
—
x ck
i ck
ns
1 i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode
(asynchronous implies that SCKT and SCKR are two different clocks)
i ck s = internal clock, synchronous mode
(synchronous implies that SCKT and SCKR are the same clock)
2 bl = bit length
wl = word length
wr = word length relative
3 SCKT(SCKT pin) = transmit clock
SCKR(SCKR pin) = receive clock
FST(FST pin) = transmit frame sync
FSR(FSR pin) = receive frame sync
HCKT(HCKT pin) = transmit high frequency clock
HCKR(HCKR pin) = receive high frequency clock
4 For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
5 The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync
signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the
second-to-last bit clock of the first word in the frame.
6 Periodically sampled and not 100% tested.
Table 46. Enhanced Serial Audio Interface Timing (continued)
No.
Characteristics1,2
Symbol
Expression2
Min.
Max.
Condition3 Unit
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