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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MCF5270CVM150R2
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋佹暩(sh霉)锛� 435/626闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU 32BIT 150MHZ 196-MAPBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 750
绯诲垪锛� MCF527x
鏍稿績铏曠悊鍣細 Coldfire V2
鑺珨灏哄锛� 32-浣�
閫熷害锛� 150MHz
閫i€氭€э細 EBI/EMI锛屼互澶恫(w菐ng)锛孖²C锛孲PI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 DMA锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 97
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 ROMless
RAM 瀹归噺锛� 64K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 1.4 V ~ 1.6 V
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 196-LBGA
鍖呰锛� 甯跺嵎 (TR)
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I2C Interface
MCF5271 Reference Manual, Rev. 2
25-16
Freescale Semiconductor
EXTB.L D1
SUBI.L #1,D1;
BNE.S NXMAR
;Not last one or second last
LAMAR BSET.B #3,I2CR
;Disable ACK
BRA NXMAR
ENMASR BCLR.B #5,I2CR
;Last one, generate STOP signal
NXMAR
MOVE.B I2DR,RXBUF
;Read data and store RTE
25.6.5 Generation of Repeated START
After the data transfer, if the master still wants the bus, it can signal another START followed by
another slave address without signalling a STOP, as in the following example.
RESTART MOVE.B I2CR,-(A7)
;Repeat START (RESTART)
BSET.B #2, (A7)
MOVE.B (A7)+, I2CR
MOVE.B CALLING,-(A7)
;Transmit the calling address, D0=R/W-
MOVE.B CALLING,-(A7)
MOVE.B (A7)+, I2DR
25.6.6 Slave Mode
In the slave interrupt service routine, software should poll the I2SR[IAAS] bit to determine if the
controller has received its slave address. If IAAS is set, software should set the transmit/receive
mode select bit (I2CR[MTX]) according to the I2SR[SRW]. Writing to the I2CR clears the IAAS
automatically. The only time IAAS is read as set is from the interrupt at the end of the address cycle
where an address match occurred; interrupts resulting from subsequent data transfers will have
IAAS cleared. A data transfer can now be initiated by writing information to I2DR for slave
transmits, or read from I2DR in slave-receive mode. A dummy read of I2DR in slave/receive mode
releases I2C_SCL, allowing the master to send data.
In the slave transmitter routine, I2SR[RXAK] must be tested before sending the next byte of data.
Setting RXAK means an end-of-data signal from the master receiver, after which software must
switch it from transmitter to receiver mode. Reading I2DR then releases I2C_SCL so that the
master can generate a STOP signal.
25.6.7 Arbitration Lost
If several devices try to engage the bus at the same time, one becomes master. Hardware
immediately switches devices that lose arbitration to slave receive mode. Data output to I2C_SDA
stops, but I2C_SCL is still generated until the end of the byte during which arbitration is lost. An
interrupt occurs at the falling edge of the ninth clock of this transfer with I2SR[IAL] = 1 and
I2CR[MSTA] = 0.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
VI-B2P-IY-F3 CONVERTER MOD DC/DC 13.8V 50W
VI-B2N-IY-F2 CONVERTER MOD DC/DC 18.5V 50W
MC9328MXLVP20R2 IC MCU I.MX 200MHZ 225-MAPBGA
VI-B2M-IY-F4 CONVERTER MOD DC/DC 10V 50W
MC9328MXLDVP20R2 IC MCU I.MX 200MHZ 225-MAPBGA
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MCF5270VM100 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU MCF5270 V2CORE 64KSRAM RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324
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