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鍨嬭櫉锛� MCF5270CVM150R2
寤犲晢锛� Freescale Semiconductor
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鎸暕鍣ㄥ瀷锛� 澶栭儴
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灏佽/澶栨锛� 196-LBGA
鍖呰锛� 甯跺嵎 (TR)
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I2C Programming Examples
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
25-13
25.6 I2C Programming Examples
The following examples show programming for initialization, signaling START, post-transfer
software response, signalling STOP, and generating a repeated START.
25.6.1 Initialization Sequence
Before the interface can transfer serial data, registers must be initialized, as follows:
1. Set I2FDR[IC] to obtain I2C_SCL frequency from the system bus clock. See
2. Update the I2ADR to define its slave address.
3. Set I2CR[IEN] to enable the I2C bus interface system.
4. Modify the I2CR to select or deselect master/slave mode, transmit/receive mode, and
interrupt-enable or not.
NOTE
If I2SR[IBB] is set when the I2C bus module is enabled, execute the
following pseudocode sequence before proceeding with normal
initialization code. This issues a STOP command to the slave device,
placing it in idle state as if it were just power-cycled on.
I2CR = 0x0
I2CR = 0xA0
dummy read of I2DR
I2SR = 0x0
I2CR = 0x0
Table 25-6. I2DR Field Description
Bit
Name
Description
7
鈥�0
DATA
I2C data. In master transmit mode, when data is written to this register, a data transfer is
initiated. The most significant bit is sent first. In master receive mode, reading this register
initiates the reception of the next byte of data. In slave mode, the same functions are
available after an address match has occurred.
Note: 1. In master transmit mode, the first byte of data written to I2DR following assertion
of I2CR[MSTA] is used for the address transfer and should comprise the calling address
(in position D7鈥揇1) concatenated with the required R/W bit (in position D0). This bit (D0)
is not automatically appended by the hardware, software must provide the appropriate
R/W bit.
Note: 2. I2CR[MSTA] generates a start when a master does not already own the bus.
I2CR[RSTA] generates a start (restart) without the master first issuing a stop (i.e., the
master already owns the bus). In order to start the read of data, a dummy read to this
register starts the read process from the slave. The next read of the I2DR register contains
the actual data.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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