
I2C System Configuration
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
25-7
its low period. Therefore, synchronized clock I2C_SCL is held low by the device with the longest
low period.
Devices with shorter low periods enter a high wait state during this time (see
Figure 25-8). When
all devices concerned have counted off their low period, the synchronized clock I2C_SCL line is
released and pulled high. There is then no difference between the device clocks and the state of the
I2C_SCL line and all the devices start counting their high periods. The first device to complete its
high period pulls the I2C_SCL line low again.
The relative priority of the contending masters is determined by a data arbitration procedure. A
bus master loses arbitration if it transmits logic "1" while another master transmits logic "0". The
losing masters immediately switch over to slave receive mode and stop driving I2C_SDA output
(see
Figure 25-7). In this case the transition from master to slave mode does not generate a STOP
condition. Meanwhile, hardware sets I2SR[IAL] to indicate loss of arbitration.
Figure 25-7. Arbitration Procedure
Figure 25-8. Clock Synchronization
I2C_SCL
I2C_SDA by
Master1
I2C_SDA by
Master2
I2C_SDA
Master 2 Loses Arbitration,
and becomes slave-receiver
Internal Counter Reset
I2C_SCL1
I2C_SCL2
I2C_SCL
Wait
Start counting high period