Edge Port Module (EPORT)
MCF5271 Reference Manual, Rev. 2
15-2
Freescale Semiconductor
NOTE
The low-power interrupt control register (LPICR) in the System
Control Module specifies the interrupt level at or above which is
needed to bring the device out of a low-power mode.
In wait and doze modes, the EPORT module continues to operate as it does in run mode. It may
be configured to exit the low-power modes by generating an interrupt request on either a selected
edge or a low level on an external pin. In stop mode, there are no clocks available to perform the
edge-detect function. Only the level-detect logic is active (if configured) to allow any low level on
the external interrupt pin to generate an interrupt (if enabled) to exit stop mode.
NOTE
The input pin synchronizer is bypassed for the level-detect logic since
no clocks are available.
15.3 Interrupt/General-Purpose I/O Pin Descriptions
All pins default to general-purpose input pins at reset. The pin value is synchronized to the rising
edge of CLKOUT when read from the EPORT pin data register (EPPDR). The values used in the
edge/level detect logic are also synchronized to the rising edge of CLKOUT. These pins use
Schmitt triggered input buffers which have built in hysteresis designed to decrease the probability
of generating false edge-triggered interrupts for slow rising and falling input signals.
When a pin is configured as an output, it is driven to a state whose level is determined by the
corresponding bit in the EPORT data register (EPDR). All bits in the EPDR are high at reset.
15.4 Memory Map/Register Definition
This subsection describes the memory map and register structure. Refer to
Table 15-2 for a
description of the EPORT memory map. The EPORT has an IPSBAR offset for base address of
0x0013_0000.
Table 15-1. Edge Port Module Operation in Low-power Modes
Low-power Mode
EPORT Operation
Mode Exit
Wait
Normal
Any IRQn Interrupt at or above level in LPICR
Doze
Normal
Any IRQn Interrupt at or above level in LPICR
Stop
Level-sensing Only
Any IRQn Interrupt set for level-sensing at or
above level in LPICR