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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� MCF5270CVM150R2
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋佹暩(sh霉)锛� 4/626闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU 32BIT 150MHZ 196-MAPBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 750
绯诲垪锛� MCF527x
鏍稿績铏曠悊鍣細 Coldfire V2
鑺珨灏哄锛� 32-浣�
閫熷害锛� 150MHz
閫i€氭€э細 EBI/EMI锛屼互澶恫(w菐ng)锛孖²C锛孲PI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 DMA锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 97
绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 ROMless
RAM 瀹归噺锛� 64K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 1.4 V ~ 1.6 V
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 196-LBGA
鍖呰锛� 甯跺嵎 (TR)
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General Operation
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
4-5
if MACSR[6:5] == -1/* signed fractional mode */
Complete Accumulator [47:0] = {ACCextn[15:8], ACCn[31:0], ACCextn[7:0]}
if MACSR[6:5] == 10/* unsigned integer mode */
Complete Accumulator[47:0] = {ACCextn[15:0], ACCn[31:0]}
The four accumulators are represented as an array, ACCn, where n selects the register.
Although the multiplier array is implemented in a four-stage pipeline, all arithmetic MAC
instructions have an effective issue rate of 1 cycle, regardless of input operand size or type.
All arithmetic operations use register-based input operands, and summed values are stored
internally in an accumulator. Thus, an additional move instruction is needed to store data in a
general-purpose register. One new feature found in EMAC instructions is the ability to choose the
upper or lower word of a register as a 16-bit input operand. This is useful in filtering operations if
one data register is loaded with the input data and another is loaded with the coefficient. Two 16-bit
multiply accumulates can be performed without fetching additional operands between instructions
by alternating the word choice during the calculations.
The EMAC has four accumulator registers versus the MAC鈥檚 single accumulator. The additional
registers improve the performance of some algorithms by minimizing pipeline stalls needed to
store an accumulator value back to general-purpose registers. Many algorithms require multiple
calculations on a given data set. By applying different accumulators to these calculations, it is
often possible to store one accumulator without any stalls while performing operations involving
a different destination accumulator.
The need to move large amounts of data presents an obstacle to obtaining high throughput rates in
DSP engines. New and existing ColdFire instructions can accommodate these requirements. A
MOVEM instruction can move large blocks of data efficiently by generating line-sized burst
references. The ability to simultaneously load an operand from memory into a register and execute
a MAC instruction makes some DSP operations such as filtering and convolution more
manageable.
The programming model includes a 16-bit mask register (MASK), which can optionally be used
to generate an operand address during MAC + MOVE instructions. The application of this register
with auto-increment addressing mode supports efficient implementation of circular data queues
for memory operands.
The additional MAC status register (MACSR) contains a 4-bit operational mode field and
condition flags. Operational mode bits control whether operands are signed or unsigned and
whether they are treated as integers or fractions. These bits also control the overflow/saturation
mode and the way in which rounding is performed. Negative, zero, and multiple overflow
condition flags are also provided.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
VI-B2P-IY-F3 CONVERTER MOD DC/DC 13.8V 50W
VI-B2N-IY-F2 CONVERTER MOD DC/DC 18.5V 50W
MC9328MXLVP20R2 IC MCU I.MX 200MHZ 225-MAPBGA
VI-B2M-IY-F4 CONVERTER MOD DC/DC 10V 50W
MC9328MXLDVP20R2 IC MCU I.MX 200MHZ 225-MAPBGA
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MCF5270VM100 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU MCF5270 V2CORE 64KSRAM RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324
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