Functional Description
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
24-21
Figure 24-19. Transmitter Timing Diagram
24.4.2.2 Receiver
When the receiver detects a high-to-low (mark-to-space) transition of the start bit on UnRXD, the
state of UnRXD is sampled eight times on the edge of the bit time clock starting one-half clock
after the transition (asynchronous operation) or at the next rising edge of the bit time clock
(synchronous operation). If UnRXD is sampled high, the start bit is invalid and the search for the
valid start bit begins again.
If UnRXD is still low, a valid start bit is assumed and the receiver continues sampling the input at
one-bit time intervals, at the theoretical center of the bit, until the proper number of data bits and
parity, if any, is assembled and one stop bit is detected. Data on the UnRXD input is sampled on
the rising edge of the programmed clock source. The lsb is received first. The data is then
transferred to a receiver holding register and USRn[RxRDY] is set. If the character is less than
eight bits, the most significant unused bits in the receiver holding register are cleared.
C11
C2
C3
Break
C4
C6
UnTXD
Transmitter
Enabled
USRn[TxRDY]
W2
WW
W
UnCTS3
UnRTS4
Manually asserted
by BIT-SET command
Manually
asserted
Start
break
C5
not
transmitted
C6
C4
Stop
break
C3
C2
C11
C1 in transmission
3 UMR2n[TxCTS] = 1
1 Cn = transmit characters
2 W = write
4 UMR2n[TxRTS] = 1
internal
module
select