Table 16-7. CSCRn Field Descriptions Bits Name Description 15" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� MCF5270CVM150R2
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 225/626闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU 32BIT 150MHZ 196-MAPBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 750
绯诲垪锛� MCF527x
鏍稿績铏曠悊鍣細 Coldfire V2
鑺珨灏哄锛� 32-浣�
閫熷害锛� 150MHz
閫i€氭€э細 EBI/EMI锛屼互澶恫(w菐ng)锛孖²C锛孲PI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 DMA锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 97
绋嬪簭瀛樺劜(ch菙)鍣ㄩ(l猫i)鍨嬶細 ROMless
RAM 瀹归噺锛� 64K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 1.4 V ~ 1.6 V
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 196-LBGA
鍖呰锛� 甯跺嵎 (TR)
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Chip Select Module
MCF5271 Reference Manual, Rev. 2
16-10
Freescale Semiconductor
Table 16-7. CSCRn Field Descriptions
Bits
Name
Description
15鈥�14
SRWS
Secondary Read Wait States. The number of wait states applied to all reads after the initial
one if properly enabled (SRSW is non-zero and CSCR[AA] = 1). The default value of this
field is secondary read wait states disabled. See Section 16.3.2, 鈥淓nhanced Wait State
Operation,鈥� for timing diagrams.
00 Secondary read wait states are disabled. Use CSCR[IWS] for all accesses.
01 0 wait states for the secondary read accesses
10 1 wait state for the secondary read accesses
11 2 wait states for the secondary read accesses
13鈥�10
IWS
Initial Wait States. The number of wait states inserted before an internal transfer
acknowledge is generated (WS = 0 inserts zero wait states, WS = 0xF inserts 15 wait
states). If AA = 0, TA must be asserted by the external system regardless of the number of
wait states generated. In that case, the external transfer acknowledge ends the cycle. An
external TA supercedes the generation of an internal TA.
9
鈥�
Reserved, should be cleared.
8
AA
Auto-acknowledge enable. Determines the assertion of the internal transfer acknowledge
for accesses specified by the chip select address.
0 No internal TA is asserted. Cycle is terminated externally.
1 Internal TA is asserted as specified by WS. Note that if AA = 1 for a corresponding CSn
and the external system asserts an external TA before the wait-state countdown asserts
the internal TA, the cycle is terminated. Burst cycles increment the address bus between
each internal termination.
7鈥�6
PS
Port size. Specifies the width of the data associated with each chip select. It determines
where data is driven during write cycles and where data is sampled during read cycles. See
00 32-bit port size. Valid data sampled and driven on D[31:0]
01 8-bit port size. Valid data sampled and driven on D[31:24]
1x 16-bit port size. Valid data sampled and driven on D[31:16]
5
BEM
Byte enable mode. Specifies the byte enable operation. Certain SRAMs have byte enables
that must be asserted during reads as well as writes. BEM can be set in the relevant CSCR
to provide the appropriate mode of byte enable in support of these SRAMs.
0BS is not asserted for read. BS is asserted for data write only.
1BS is asserted for read and write accesses.
4
BSTR
Burst read enable. Specifies whether burst reads are used for memory associated with
each CSn.
0 Data exceeding the specified port size is broken into individual, port-sized non-burst
reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads.
1 Enables data burst reads larger than the specified port size, including longword reads
from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8-, 16-, and
32-bit ports.
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