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參數(shù)資料
| 型號(hào)： | MCC5E0RX266WB0B |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 266 MHz, RISC PROCESSOR, CBGA840 |
| 封裝： | 31 X 31 MM, 3.55 MM HEIGHT, 1 MM PITCH, CERAMIC, FCBGA-840 |
| 文件頁數(shù)： | 95/120頁 |
| 文件大?。?/td> | 1711K |
| 代理商： | MCC5E0RX266WB0B |
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76
CHAPTER 3: ELECTRICAL SPECIFICATIONS
C5ENPB0-DS REV 05
MOTOROLA GENERAL BUSINESS INFORMATION
Power Sequencing
It is intended that the VDD33/VDDT/VDDF and VDD rails are sequenced to their final value
together. VDD33, VDDT and VDDF must be above VDD at all times to prevent internal
parasitic diodes from turning on and possibly damaging the device. VDD must be brought
to its final value within 100ms of sequencing on VDD33, VDDT and VDDF. During this
100ms, significant current may be drawn by the three IO supplies (up to 30A total) until
VDD is asserted to reset the IO drivers. To minimize this current draw during power-on, it
is recommended that this sequencing time be minimized in the power supply design.
It is also required that SCLK, SCLKX, TCLKI, PCLK, MDCLK, FTXCLK, and FRXCLK be running
or begin running during power sequencing to propagate reset inside the C-5e NP. Figure 9
indicates the relationship between the clocks and PRSTX. There is no requirement that the
asserting and deasserting edges of PRSTX be synchronous to the clocks. Reset must be
asserted within 100
s of power initiation. Typically, reset is held low during power
initiation.
Figure 9 Bringup Clock Timing Diagram
TCLKI, PCLK,
SCLK, SCLKX,
MDCLK, FTXCLK,
FRXCLK
PRSTX
≥1ms
≥100
s
(
)
≤100
s
VDD, VDD33,
VDDT, VDDF
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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