參數(shù)資料
型號： MCC5E0RX266WB0B
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 266 MHz, RISC PROCESSOR, CBGA840
封裝： 31 X 31 MM, 3.55 MM HEIGHT, 1 MM PITCH, CERAMIC, FCBGA-840
文件頁數(shù)： 38/120頁
文件大?。?/td> 1711K
代理商： MCC5E0RX266WB0B
24
CHAPTER 1: FUNCTIONAL DESCRIPTION
C5ENPB0-DS REV 05
MOTOROLA GENERAL BUSINESS INFORMATION
PROM Interface — Allows the XP to boot from nonvolatile, flash memory. The PROM
interface is a low-speed, serial I/O port that runs at 1/
2 to
1/
16 the core clock rate. The
maximum PROM size addressable is 4MBytes, and must use a “by 16” part. External
board logic is required to perform serial-to-parallel conversion for PROM address
outputs and parallel-to-serial conversion for PROM data inputs.
Fabric Processor
The Fabric Processor (FP) acts as a high-speed network interface port with advanced
functionality. It allows the C-5e NP to interface to an application-specific switching
solution internal to your design. The FP port supports the bidirectional transfer of
segments from the C-5e NP to a hardware interface that provides connectivity to other
network processors or other similar line processing hardware. There are numerous
parameters that can be configured within the FP to allow the interface to be adapted to
different fabric protocols. The FP can be configured to conform to seven (7) different
fabric interfaces that include: CSIX-L1, UTOPIA-1, -2, -3, PRIZMA, Power X(CSIX-L0), and
UTOPIA3 like to M-5.
The FP can be configured to run at any frequency up to 125MHz, with the receive and
transmit data buses up to 32 bits wide. This allows a wide range of supported bandwidths
to and from the switching fabric, all the way up to 4000 Mbps full duplex bandwidth.
Buffer Management Unit
The Buffer Management Unit (BMU) interfaces the C-5e NP to external pipeline
architecture, Single Data Rate Synchronous DRAM. The external memory is partitioned
and used as buffers for receiving and transmitting data between CPs, the FP, and the XP. It
is also used as second level storage in the XP memory hierarchy.
The interface to an array of SDRAM chips is 139bits wide, composed of 128 data bits, two
internal control bits, and nine SECDED (single error correction-double error detection) ECC
(error correction code) bits. The interface is compliant with the PC100 standard and
operates at up to 133MHz with 3.3V LVTTL-compatible inputs and outputs. The refresh
period, Trcd, Tcas, Trp, Tmrd, and Trc are configurable via boot time configuration (see the
C-5e/C-3e Network Processor Architecture Guide (part number C5EC3EARCH-RM) for more
details).
The C-5e NP non-configurable interface transfers four beats of data for each read and
write using a sequential burst type. In addition, the C-5e NP uses an auto-refresh mode for
the RAM’s.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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