參數(shù)資料
型號(hào): MCC5E0RX266WB0B
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 266 MHz, RISC PROCESSOR, CBGA840
封裝: 31 X 31 MM, 3.55 MM HEIGHT, 1 MM PITCH, CERAMIC, FCBGA-840
文件頁(yè)數(shù): 49/120頁(yè)
文件大?。?/td> 1711K
代理商: MCC5E0RX266WB0B
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34
CHAPTER 2: SIGNAL DESCRIPTIONS
C5ENPB0-DS REV 05
MOTOROLA GENERAL BUSINESS INFORMATION
DS1/T1 Framer Interface Configuration
Table 8 describes the serial framer interface signals. For each CP (0-15), you can
implement one serial Framer interface.
10/100 Ethernet (RMII) Configuration
Table 9 describes the 10/100BASE-T Ethernet Reduced Media Independent Interface
(RMII) signals. For each CP (0-15), you can implement one 10/100 Ethernet interface.
Table 8 DS1/T1 Framer Interface Signals
SIGNAL NAME*
PIN #
TOTAL
TYPE
I/O
LABEL
SIGNAL DESCRIPTION
CPn_0
1
LVTTL
O
PD
TCLK
Transmit Clock (1.544MHz)
CPn_1
1
LVTTL
I
PU
RCLK
Receive Clock (1.544MHz)
CPn_2
1
LVTTL
O
PD
TData
Transmit Data
CPn_3
1
LVTTL
O
PU
TFrame
Transmit Frame Synchronization
CPn_4
1
LVTTL
I
PD
RData
Receive Data
CPn_5
1
LVTTL
I
PU
RFrame
Receive Frame Synchronization
CPn_6
1
nc
ncPU nc
nc
TOTAL PINS
7
* n can be from 0 to 15. See Table 7.
Reference Table 7 for pin numbers for the actual cluster(s) you are configuring.
Table 9 10/100 Ethernet Signals
SIGNAL NAME*
PIN #
TOTAL
TYPE
I/O
LABEL
SIGNAL DESCRIPTION
CPn_0
1
LVTTL
O
PD
REF_CLK
Transmit and Receive Clock (50MHz)
CPn_1
1
LVTTL
I
PU
CRS_DV
Carrier Sense (CRS)/ Receive Data Valid (RX_DV). CRS indicates that
traffic is on the link, and is asserted if the signal is a 1 or an
alternating 1010... RX_DV indicates that a receive frame is in
progress and the data present on the RXD pins is valid. It is
asserted if this signal is a 1 for more than one cycle.
CPn_2
1
LVTTL
O
PD
TXD(0)
Transmit Data 0 (first on wire)
CPn_3
1
LVTTL
O
PU
TXD(1)
Transmit Data 1 (second on wire)
CPn_4
1
LVTTL
I
PD
RXD(0)
Receive Data 0 (first on wire)
CPn_5
1
LVTTL
I
PU
RXD(1)
Receive Data 1 (second on wire)
CPn_6
1
LVTTL
OPU
TX_EN
Transmit Enable. When asserted, the data on TXD is encoded and
transmitted on the twisted pair cable.
TOTAL PINS
7
* n can be from 0 to 15. See Table 7.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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