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參數(shù)資料
| 型號： | MC9S12UF32PU |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 60 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | LQFP-100 |
| 文件頁數(shù)： | 90/128頁 |
| 文件大?。?/td> | 1785K |
| 代理商： | MC9S12UF32PU |
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System on a Chip Guide — 9S12UF32DGV1/D V01.05
64
Freescale Semiconductor
2.4.42 PR[3] / CFA[6] / TXD — Port R I/O Pins [3]
PR[3] is general purpose input or output pin. When enabled in the CFHC module, the PR[3] pin becomes
the Compact Flash address pin, CFA[6]. This port pin can be configured as either CF address or general
purpose I/O pin in CFHC module. When the CFHC module is not enabled or this pin is released, it can
also be configured as the TXD pin when the SCI module is enabled. While in reset and immediately out
of reset PR[3] pin is configured as high impedance input pin. Consult the Serial Communication Interface
(SCI), the Port Integration Module (PIM) PIM_9UF32 Block Guide and the CFHC Block Guide for
information about pin configurations.
2.4.43 PR[7:4] / CFA[10:7] / IOC[7:4] — Port R I/O Pins [7:4]
PR[7:4] are general purpose input or output pins. When enabled in the CFHC module, the PR[7:4] pins
become the Compact Flash address pins, CFA[10:7]. Individual port pins can be configured as either CF
address or released for other function in CFHC module. When the CFHC module is not enabled or these
pins are released, they can also be configured as the TIM input capture or output compare pins IOC[7:4]
when the TIM module is enabled. While in reset and immediately out of reset PR[7:4] pins are configured
as high impedance input pins. Consult the Port Integration Module (PIM) PIM_9UF32 Block Guide, the
CFHC Block Guide and the TIM_16B8C Block Guide for information about pin configurations.
2.4.44 PS7 / CFRDY(CFIREQ) / ATAINTQ — Port S I/O Pin 7
PS7 is a general purpose input or output pin. When the compact flash host controller (CFHC) is enabled
PS7 becomes the compact flash ready or interrupt pin, CFRDY/IREQ, depending on the operating mode.
When the CFHC is not enabled, it can be configured as the ATA interrupt pin, ATAINTQ, when the ATA5
host controller (ATA5HC) is enabled. While in reset and immediately out of reset the PS7 pin is
configured as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9UF32 Block
Guide, the CFHC Block Guide and the ATA5HC Block Guide for information about pin configurations.
2.4.45 PS6 / CFWE / ATADMARQ — Port S I/O Pin 6
PS6 is a general purpose input or output pin. When the compact flash host controller (CFHC) is enabled
PS6 becomes the compact flash write enable pin, CFWE. When the CFHC is not enabled, it can be
configured as the ATA DMA request pin, ATADMARQ, when the ATA5 host controller (ATA5HC) is
enabled. While in reset and immediately out of reset the PS6 pin is configured as a high impedance input
pin. Consult the Port Integration Module (PIM) PIM_9UF32 Block Guide, the CFHC Block Guide and the
ATA5HC Block Guide for information about pin configurations.
2.4.46 PS5 / CFIOWR / ATAIOWR — Port S I/O Pin 5
PS5 is a general purpose input or output pin. When the compact flash host controller (CFHC) is enabled
PS5 becomes the compact flash I/O write pin, CFIOWR. When the CFHC is not enabled, it can be
configured as the ATA I/O write pin, ATAIOWR, when the ATA5 host controller (ATA5HC) is enabled.
While in reset and immediately out of reset the PS5 pin is configured as a high impedance input pin.
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