參數(shù)資料
型號: MC9S12UF32PU
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 60 MHz, MICROCONTROLLER, PQFP100
封裝: LQFP-100
文件頁數(shù): 42/128頁
文件大?。?/td> 1785K
代理商: MC9S12UF32PU
System on a Chip Guide — 9S12UF32DGV1/D V01.05
20
Freescale Semiconductor
- Used as a contiguous 3.5k byte SRAM with misaligned access support
- Configurable to 1084 byte SRAM and 2000 x 10 bit SRAM for Smartmedia logical to physical
address translation and parity generation/checking support.
1.5K byte Queue RAM
- SRAM used as USB endpoint buffer, access is arbitrated by IQUE module
8-channel Timer (TIM)
Eight input capture/output compare channels
Clock prescaling
16-bit counter
16-bit pulse accumulator
Serial Interface
Asynchronous serial communication interface (SCI)
Internal Regulator (VREG_U)
Input voltage range from 4.25V to 5.5V
Separate Regulation circuits
- 2.5V Regulator for Core Logic and memory
- 3.3V Regulator for USB2.0 physical layer interface
- 3.3V Regulator with off-chip NMOS driver for I/O and memory cards
Power on Reset detection
Integrated Queue Controller (IQUE)
Provide block data transfer without CPU intervention
Four independent queue channels for data transfer between Queue RAM and peripherals
Unified Queue RAM Memory which can be allocated to different usb endpoints and storage
interface module
Programming model allows implementation of double buffering for maximum burst data
throughput of 60M bytes per second between USB20D6E2F and one of the Storage Interfaces
Universal Serial Bus 2.0 (USB20D6E2F)
Intergrated USB2.0 Physical Layer Transceiver (USB20PHY) for High speed and Full Speed
operations
USB 2.0 Serial Interface Engine (USB20SIE) for High Speed and Full Speed operations
compatible
- Endpoint 0 for Control IN and OUT operation
- Endpoint 2 and 3 are configurable for Bulk, ISO or Interrupt IN/OUT operation
- Endpoint buffer with programmable size residing in Queue RAM for endpoints 4 and 5
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