參數(shù)資料
型號: MC9S12UF32PU
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 60 MHz, MICROCONTROLLER, PQFP100
封裝: LQFP-100
文件頁數(shù): 19/128頁
文件大?。?/td> 1785K
代理商: MC9S12UF32PU
115
Freescale Semiconductor
System on a Chip Guide — 9S12UF32DGV1/D V01.05
A.4 Reset, Oscillator and PHY
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
USB Physical Layer (PHY).
A.4.1 Startup
Table A-12 summarizes several startup characteristics explained in this section. Detailed description of
the startup behavior can be found in the Clock and Reset Generator (CRG_U) Block User Guide.
A.4.1.1 POR
The release level VPORR and the assert level VPORA are derived from the VDD Supply. They are also valid
if the device is powered externally. After releasing the POR reset, the oscillator is started.
A.4.1.2 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG_U Flags Register has not been set.
A.4.1.3 External Reset
When external reset is asserted for a time greater than PWRSTL, the CRG_U module generates an internal
reset, and the CPU starts fetching the reset vector if there was an oscillation before reset.
A.4.1.4 Stop Recovery
Out of STOP, the controller can be woken up by an external interrupt.
Table A-12 Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
C
Rating
Symbol
Min
Typ
Max
Unit
1
T
POR release level
VPORR
2.07
V
2
T
POR assert level
VPORA
0.97
V
3
D
Reset input pulse width, minimum input time
PWRSTL
2
tosc
4
D
Startup from Reset
nRST
192
196
nosc
5D
Interrupt pulse width, IRQ edge-sensitive
mode
PWIRQ
20
ns
6
D
Wait recovery startup time
tWRS
14
tcyc
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