Internal Clock Generator (ICG) Module
MC9S08GB/GT Data Sheet, Rev. 2.3
104
Freescale Semiconductor
7.3.1.3
Stop/Off Mode Recovery
UpontheCPUexitingstopmodeduetoaninterrupt,thepreviouslysetcontrolbitsarevalidandthesystem
clock feed resumes. If FEE is selected, the ICG will source the internal reference until the external clock
is stable. If FBE is selected, the ICG will wait for the external clock to stabilize before enabling ICGOUT.
Upon the CPU exiting stop mode due to a reset, the previously set ICG control bits are ignored and the
default reset values applied. Therefore the ICG will exit stop in SCM mode configured for an
approximately 8 MHz DCO output (4 MHz bus clock) with trim value maintained. If using a crystal, 4096
clocks are detected prior to engaging ICGERCLK. This is incorporated in crystal start-up time.
7.3.2
Self-Clocked Mode (SCM)
Self-clocked mode (SCM) is the default mode of operation and is entered when any of the following
conditions occur:
After any reset.
Exiting from off mode when CLKS does not equal 10. If CLKS = X1, the ICG enters this state
temporarily until the DCO is stable (DCOS = 1).
CLKS bits are written from X1 to 00.
CLKS = 1X and ICGERCLK is not detected (both ERCS = 0 and LOCS = 1).
Inthisstate,theFLLloopisopen.TheDCOison,andtheoutputclocksignalICGOUTfrequencyisgiven
by f
ICGDCLK
/ R. The ICGDCLK frequency can be varied from 8 MHz to 40 MHz by writing a new value
into the filter registers (ICGFLTH and ICGFLTL). This is the only mode in which the filter registers can
be written.
If this mode is entered due to a reset, f
ICGDCLK
will default to f
Self_reset
which is nominally 8 MHz. If this
mode is entered from FLL engaged internal, f
ICGDCLK
will maintain the previous frequency.If this mode
is entered from FLL engaged external (either by programming CLKS or due to a loss of external reference
clock),f
ICGDCLK
willmaintainthepreviousfrequency,butICGOUTwilldoubleiftheFLLwasunlocked.
If this mode is entered from off mode, f
ICGDCLK
will be equal to the frequency of ICGDCLK before
entering off mode. If CLKS bits are set to 01 or 11 coming out of the Off state, the ICG enters this mode
until ICGDCLK is stable as determined by the DCOS bit. Once ICGDCLK is considered stable, the ICG
automatically closes the loop by switching to FLL engaged (internal or external) as selected by the CLKS
bits.