
MC9S08GB/GT Data Sheet, Rev. 2.3
10
Freescale Semiconductor
Section Number
Title
Page
Chapter 7
Internal Clock Generator (ICG) Module
Introduction .....................................................................................................................................99
7.1.1
Features ..........................................................................................................................100
7.1.2
Modes of Operation .......................................................................................................101
External Signal Description ..........................................................................................................101
7.2.1
Overview ........................................................................................................................101
7.2.2
Detailed Signal Descriptions .........................................................................................102
7.2.2.1
EXTAL— External Reference Clock / Oscillator Input ...............................102
7.2.2.2
XTAL— Oscillator Output ...........................................................................102
7.2.3
External Clock Connections ..........................................................................................102
7.2.4
External Crystal/Resonator Connections .......................................................................102
Functional Description ..................................................................................................................103
7.3.1
Off Mode (Off) ..............................................................................................................103
7.3.1.1
BDM Active .................................................................................................103
7.3.1.2
OSCSTEN Bit Set .........................................................................................103
7.3.1.3
Stop/Off Mode Recovery ..............................................................................104
7.3.2
Self-Clocked Mode (SCM) ............................................................................................104
7.3.3
FLL Engaged, Internal Clock (FEI) Mode ....................................................................105
7.3.3.1
FLL Engaged Internal Unlocked ..................................................................105
7.3.3.2
FLL Engaged Internal Locked ......................................................................106
7.3.4
FLL Bypassed, External Clock (FBE) Mode ................................................................106
7.3.5
FLL Engaged, External Clock (FEE) Mode ..................................................................106
7.3.5.1
FLL Engaged External Unlocked .................................................................106
7.3.5.2
FLL Engaged External Locked .....................................................................107
7.3.6
FLL Lock and Loss-of-Lock Detection .........................................................................107
7.3.7
FLL Loss-of-Clock Detection ........................................................................................107
7.3.8
Clock Mode Requirements ............................................................................................108
7.3.9
Fixed Frequency Clock ..................................................................................................109
Initialization/Application Information ..........................................................................................110
7.4.1
Introduction ....................................................................................................................110
7.4.2
Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz .........................112
7.4.3
Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz ............................113
7.4.4
Example #3: No External Crystal Connection, 5.4 MHz Bus Frequency .....................114
7.4.5
Example #4: Internal Clock Generator Trim .................................................................116
ICG Registers and Control Bits .....................................................................................................117
7.5.1
ICG
Control Register 1 (
ICG
C1) ......................................................................118
7.5.2
ICG
Control Register 2 (
ICG
C2) ......................................................................119
7.5.3
ICG
Status Register 1 (
ICG
S1)
.................................................................................120
7.5.4
ICG
Status Register 2 (
ICG
S2) ........................................................................122
7.5.5
ICG
Filter Registers (
ICG
FLTU, ICGFLTL) .......................................................122
7.5.6
ICG
Trim Register (
ICG
TRM) ...........................................................................123
7.1
7.2
7.3
7.4
7.5