參數(shù)資料
型號(hào)： MC92602ZTA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196
封裝： 15 X 15 MM, 1.60 MM HEIGHT, 1 MM PITCH, MAPBGA-196
文件頁(yè)數(shù)： 39/102頁(yè)
文件大?。?/td> 1581K
代理商： MC92602ZTA
MOTOROLA
Chapter 3. Receiver
3-13
Functional Description
For example, if the transmitter is sending data at a rate faster than the receiver, then a
shortened cycle is generated as needed to track the incoming data rate. Alternately, if the
transmitter is running slower than the receiver, then a long cycle is generated.
The recovered clock duty cycle may be reduced or increased by 2.5% in order to match the
transmitter frequency. For example, if the reference clock frequency is 125 MHz, this
means that the minimum recovered clock cycle time is 7.8 ns and the maximum recovered
clock cycle is 8.2 ns.
NOTE
Devices that interface to the MC92602 and run in a recovered
clock mode must be able to tolerate this modulated clock.
All receiver channel outputs are source synchronous with their respective RECV_x_CLK
outputs. If the receivers are being operated in word synchronization mode (WSE = high),
the data for all four receivers are timed relative to link A’s recovered clock RECV_A_CLK.
In word synchronization all four clocks are derived from channel A and may be used if
necessary.
When operating in the recovered clock timing mode, the addition or deletion of idles is
inappropriate.
NOTE
If RCCE is asserted (recovered clock timing mode), the
add/delete idle enable (ADIE) signal must be low.
3.3.7.2
Reference Clock Timing Mode
Data is timed relative to the local reference clock frequency when RCCE is low.
Synchronization between the recovered clock and the reference clock is handled by the
receiver interface. Frequency offset between the transmitter’s reference clock and the
receiver’s reference clock causes overrun/underrun situations. Overrun occurs when the
transmitter is running faster than the receiver. Underrun occurs when the transmitter is
running slower than the receiver.
In an overrun situation, data must be dropped in order to maintain synchronization between
the clock domains. If the control signal, add drop idle enable, ADIE, is asserted high, the
receiver interface searches for a pair of idle bytes to drop when overrun is imminent. Two
idle bytes are dropped to assure that running disparity is not affected. If sufficient idle
patterns are not available to drop, receiver overrun may occur. When overrun occurs, the
‘overrun’ error is reported, as described in Section 3.3.6.3, “Receiver Interface Error
Codes,” for a 1-byte clock period and 1 character of data is dropped. An overrun error is
also reported if ADI mode is disabled and overrun occurs, even if idles are available to
drop.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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