參數(shù)資料
型號(hào)： MC92602ZTA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196
封裝： 15 X 15 MM, 1.60 MM HEIGHT, 1 MM PITCH, MAPBGA-196
文件頁(yè)數(shù)： 13/102頁(yè)
文件大小： 1581K
代理商： MC92602ZTA
1-2
MC92602 SerDes Reference Manual
MOTOROLA
Features
excellent board density without making unreasonable signal integrity demands of the ASIC
device to which it interfaces.
An IEEE Std 802.3-2002 compatibility mode has been included to enable non-intrusive
operation with packet streams. And finally, IEEE Std 1149.1 JTAG boundary scan and
built-in PRBS generator/analyzers are provided for board test support.
1.2
Features
The main features of the MC92602 are as follows:
General features:
— Four full-duplex differential data links
— Selectable speed range: 1.25 or 0.625 Gbaud
— Rate adaption compatibility with packet data streams
— Context sensitive rate adaption during receipt of idle and data code groups
— Supports Jumbo frame lengths of up to 16 Kbytes
— Supports frame bursting
— Differential reference clock input with single-ended clock input option
— Low power, approximately 1.2 W under typical conditions, while operating all
transceivers at full speed.
— Unused transceiver channels may be individually disabled
— IEEE Std 1149.1 JTAG support and full-speed built-in self-test (BIST) functions
— Package: 196-pin MAPBGA (15
× 15 mm body size, 1.0 mm ball pitch)
Data interface features:
— Internal 8B10B encoder/decoder that may be bypassed in ten-bit interface mode
where external coding is used.
— Double data rate (DDR), source synchronous, 4- and 5-bit HSTL Class-I parallel
interfaces.
— Transmit data clock is selectable between per-channel transmit clock or channel
‘A’ transmit clock.
— Link-to-link synchronization supports aligned, multi-channel, word transfers.
The synchronization mechanism tolerates up to 40 bit-times of link-to-link
media skew.
— Selectable idle character alignment mode enables aligned transfers with
automatic realignment or unaligned data transfers (if in 10-bit mode).
— Received data may be clocked to the recovered clock or to the reference clock
frequencies.
— Compatibility mode enables non-intrusive operation with packet data streams.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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