參數(shù)資料
型號: MC92602ZTA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196
封裝: 15 X 15 MM, 1.60 MM HEIGHT, 1 MM PITCH, MAPBGA-196
文件頁數(shù): 34/102頁
文件大小: 1581K
代理商: MC92602ZTA
MOTOROLA
Chapter 3. Receiver
3-9
Functional Description
3.3.5
8B/10B Decoder
The 8B/10B decoder takes the 10-bit character from the transition tracking loop and
decodes it according to the 8B/10B coding standard [1,2]. The decoder does two types of
error checking. First, it checks that all characters are a legal member of the 8B/10B coding
space. The decoder also checks for running disparity errors. If the running disparity exceeds
the limits set in the 8B/10B coding standard then a disparity error is generated.
An illegal character or disparity error results in a ‘code error’ or ‘disparity error’ being
reported as described in Section 3.3.6.3, “Receiver Interface Error Codes.” It is difficult to
determine the exact byte that causes a disparity error, so the error should not be associated
with a particular received byte. It is rather, a general indicator of the improper operation of
the link. Its intended use is for the system to monitor link reliability.
The 8B/10B decoder is bypassed when operating in ten-bit interface mode (TBIE set high.)
Add/delete idle
ADIE
High
When enabled, allows the receiver to add/delete idle
patterns in order to maintain word synchronization.
This is the recommended operating mode when the
reference clock is used to time the receiver interface
(RCCE set low) and there is a frequency offset
between the transmitter and receiver. Idles are added
or dropped to maintain word alignment.
Compatibility mode
COMPAT
Low
Word synchronization is not supported in
compatibility mode.
Ten-bit interface
TBIE
N/A
When enabled, the idle character must be part of the
TBI code set. When disabled, the idle is naturally
supported by the 8B/10B codes.
Recovered clock
RCCE
N/A
Does not affect word synchronization.
Receiver A recovered
clock select
RECV_REF_A
High
(if RCCE is high)
RECV_REF_A must be high if RCCE is enabled. The
receiver A’s recovered clock must be used for all
receivers.
The data at the receiver interfaces will be skewed if
the individual receiver recovered clocks are used to
time the receiver interfaces.
Half-speed enable
HSE
N/A
Does not affect word synchronization.
Table 3-3. Word Synchronization Settings (continued)
Mode
Signals
Recommended
State
Description
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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