參數(shù)資料
型號: MC92602ZTA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196
封裝: 15 X 15 MM, 1.60 MM HEIGHT, 1 MM PITCH, MAPBGA-196
文件頁數(shù): 32/102頁
文件大?。?/td> 1581K
代理商: MC92602ZTA
MOTOROLA
Chapter 3. Receiver
3-7
Functional Description
‘Not Byte Sync’ as described in Section 3.3.7.1, “Recovered Clock Timing Mode,
for a few recovered clocks to allow the receiver FIFO to re-align. Data will be lost
while “Not Byte Sync” status is being reported. The actual number of clocks that
“Not Byte Sync” will be reported will vary depending on the number of bytes in the
FIFO when realignment occurs.
Alignment is also lost when the number of received characters with 8B/10B coding
errors outnumbers the non-errored characters by four. Credit for non-errored
characters in excess of errored characters is limited to four, such that alignment is
lost after four consecutive errored characters. Misalignment detection of this type is
not available in TBI mode. The receiver restarts its alignment procedure and halts
data flow until a new alignment is established.
Alignment is lost when DROP_SYNC followed by XCVR_x_DISABLE are both
asserted high for at least two clocks (see Section 2.3.4, “Transceiver Disable,” for
details on performing drop sync). Current alignment is invalidated, the receiver
restarts its alignment procedure and halts data flow until a new alignment is
achieved.
When establishing byte alignment, or when data flow is halted due to misalignment, the
‘Not Byte Sync’ error is reported as described in Section 3.3.6.3, “Receiver Interface Error
3.3.3.2
Non-Aligned
In this mode no attempt is made to align the incoming data stream. The bits are simply
accumulated into 10-bit characters and forwarded. This mode should be used only with
ten-bit interface mode, TBIE set high, and with word synchronization disabled, WSE set
low.
3.3.4
Word Synchronization
The four receivers in the MC92602 can be used cooperatively to receive aligned
multi-channel
word
transfers.
Word
alignment
is
enabled
by
asserting
word
synchronization enable input, WSE, high.
Word synchronization is possible in byte interface mode or in TBI mode. However, word
synchronization is dependent on the detection of simultaneously transmitted word
synchronization events that contain idle characters. Therefore, if operating in TBI mode,
the idle character must be a supported member of the code set.
If WSE is high, then all enabled receivers (those that have XCVR_x_DISABLE set low)
will be aligned into a 16-, 24-, or 32-bit word (depending on the states of the various
XCVR_x_DISABLE signals). If the receiver on channel A is disabled, then do not select
the clock from channel A as the recovered clock for all the channels.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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