參數(shù)資料
型號(hào)： MC7447RX1000NBR2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1000 MHz, RISC PROCESSOR, CBGA360
封裝： 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, FLIP CHIP, BGA-360
文件頁(yè)數(shù)： 36/87頁(yè)
文件大?。?/td> 1586K
代理商： MC7447RX1000NBR2
MOTOROLA
MPC7457 RISC Microprocessor Hardware Specifications
41
Package Description
1.8
Package Description
The following sections provide the package parameters and mechanical dimensions for the CBGA package.
1.8.1
Package Parameters for the MPC7447, 360 CBGA
The package parameters are as provided in the following list. The package type is 25
× 25 mm, 360-lead
ceramic ball grid array (CBGA).
Package outline
25
× 25 mm
Interconnects
360 (19
× 19 ball array – 1)
Pitch
1.27 mm (50 mil)
Minimum module height
2.72 mm
Maximum module height
3.24 mm
Ball diameter
0.89 mm (35 mil)
VDD_SENSE[0:1]
G11, J8
—
N/A
17
Notes:
1. OVDD supplies power to the processor bus, JTAG, and all control signals except the L3 cache controls (L3CTL[0:1]);
GVDD supplies power to the L3 cache interface (L3ADDR[0:17], L3DATA[0:63], L3DP[0:7], L3_ECHO_CLK[0:3],
and L3_CLK[0:1]) and the L3 control signals L3_CNTL[0:1]; and VDD supplies power to the processor core and
the PLL (after filtering to become AVDD). For actual recommended value of Vin or supply voltages, see Table 4.
2. Unused address pins must be pulled down to GND.
3. These pins require weak pull-up resistors (for example, 4.7 k
) to maintain the control signals in the negated state
after they have been actively negated and released by the MPC7457 and other bus masters.
4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at
HRESET going high.
5. This signal must be negated during reset, by pull up to OVDD or negation by HRESET (inverse of HRESET), to
ensure proper operation.
6. To program the processor interface I/O voltage, connect BVSEL to either GND (selects 1.8 V) or to HRESET (selects
2.5 V). To program the L3 interface, connect L3VSEL to either GND (selects 1.8 V) or to HRESET (selects 2.5 V).
If used, pull-down resistors should be less than 250
.
7. Internal pull up on die.
8. Ignored in 60x bus mode.
9. These signals must be pulled down to GND if unused or if the MPC7457 is in 60x bus mode.
10.These input signals for factory use only and must be pulled down to GND for normal machine operation.
11.Power must be supplied to GVDD, even when the L3 interface is disabled or unused.
12.This test signal is recommended to be tied to HRESET; however, other configurations will not adversely affect
performance.
13.These input signals are for factory use only and must be pulled up to OVDD for normal machine operation.
14.These signals are for factory use only and must be left unconnected for normal machine operation.
15.This pin can externally cause a performance monitor event. Counting of the event is enabled via software.
16.This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper
operation.
17.These pins are internally connected to VDD. They are intended to allow an external device to detect the core voltage
level present at the processor core. If unused, they must be connected directly to VDD or left unconnected.
Table 17. Pinout Listing for the MPC7457, 483 CBGA Package (continued)
Signal Name
Pin Number
Active
I/O
I/F Select 1
Notes
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