參數(shù)資料
型號: MC7447RX1000NBR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1000 MHz, RISC PROCESSOR, CBGA360
封裝: 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, FLIP CHIP, BGA-360
文件頁數(shù): 21/87頁
文件大?。?/td> 1586K
代理商: MC7447RX1000NBR2
28
MPC7457 RISC Microprocessor Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
Table 14. L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs
At recommended operating conditions. See Table 4.
Parameter
Symbol
All Speed Grades
Unit
Notes
Min
Max
L3_CLK rise and fall time
tL3CR, tL3CF
—0.75
ns
1, 2
Setup times: Data and parity
tL3DVEH
0.1
ns
2, 3
Input hold times: Data and parity
tL3DXEH
0.7
ns
2, 3
Valid times: Data and parity
tL3CHDV
2.5
ns
2, 4, 5, 6
Valid times: All other outputs
tL3CHOV
1.8
ns
5, 6
Output hold times: Data and parity
tL3CHDX
1.4
ns
2, 4, 5, 6
Output hold times: All other outputs
tL3CHOX
1.0
ns
2, 5, 6
L3_CLK to high impedance: Data and parity
tL3CHDZ
—3.0
ns
2
L3_CLK to high impedance: All other outputs
tL3CHOZ
—3.0
ns
2
Notes:
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD.
2. Timing behavior and characterization are currently being evaluated.
3. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising
edge of the input L3_ECHO_CLKn (see Figure 10). Input timings are measured at the pins.
4. All output specifications are measured from the midpoint voltage of the rising edge of L3_CLKn to the midpoint of
the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive
50-
load (see Figure 10).
5. tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually
launched by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output valid
and output hold times such that the specified output signal will be valid for approximately one L3_CLK period
starting three-fourths of a clock before the edge on which the SRAM will sample it and ending one-fourth of a clock
period after the edge it will be sampled.
Specifications” for more information.
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