參數(shù)資料
型號: MC68HCP11A1CFN3
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: HCMOS Single-Chip Microcontroller
中文描述: 8-BIT, EEPROM, 3 MHz, MICROCONTROLLER, PQCC52
封裝: PLASTIC, LCC-52
文件頁數(shù): 114/158頁
文件大?。?/td> 776K
代理商: MC68HCP11A1CFN3
MOTOROLA
10-16
CPU, ADDRESSING MODES, AND INSTRUCTION SET
MC68HC11A8
TECHNICAL DATA
10
2-20
TEST
Infinite
1
2
3
4
5 – n
Opcode Address
Opcode Address + 1
Opcode Address + 1
Opcode Address + 2
Previous Address + 1
1
1
1
1
1
Opcode ($00)
Irrelevant Data
Irrelevant Data
Irrelevant Data
Irrelevant Data
Table 10-3 Cycle-by-Cycle Operation — Immediate Mode
Reference
Number*
3-1
Address Mode
and Instructions
ADCA, ADCB, ADDA,
ADDB, ANDA, ANDB,
BITA, BITB, CMPA,
CMPB, EORA, EORB,
LDAA, LDAB, ORAA,
ORAB, SBCA, SBCB,
SUBA, SUBB,
LDD, LDS, LDX
Cycles Cycle
#
1
2
Address Bus
R/W
Line
1
1
Data Bus
2
Opcode Address
Opcode Address + 1
Opcode
Operand Data
3-2
3
1
2
3
1
2
3
4
1
Opcode Address
Opcode Address + 1
Opcode Address + 2
Opcode Address
Opcode Address + 1
Opcode Address + 2
$FFFF
Opcode Address
1
1
1
1
1
1
1
1
Opcode
Operand Data (High Byte)
Operand Data (Low Byte)
Opcode
Operand Data (High Byte)
Operand Data (Low Byte)
Irrelevant Data
Opcode (Page Select Byte)
($18)
Opcode (Second Byte) ($EC)
Operand Data (High Byte)
Operand Data (Low Byte)
Opcode (Page Select Byte)
Opcode (Second Byte)
Operand Data (High Byte)
Operand Data (Low Byte)
Irrelevant Data
3-3
ADDD, CPX, SUBD
4
3-4
LDY
4
2
3
4
1
2
3
4
5
Opcode Address + 1
Opcode Address + 2
Opcode Address + 3
Opcode Address
Opcode Address + 1
Opcode Address + 2
Opcode Address + 3
$FFFF
1
1
1
1
1
1
1
1
3-5
CPD, CPY
5
*The reference number is given to provide a cross-reference to Table 10-1.
Table 10-4 Cycle-by-Cycle Operation — Direct Mode (Sheet 1 of 2)
Reference
Number*
4-1
Address Mode
and Instructions
ADCA, ADCB, ADDA,
ADDB, ANDA, ANDB,
BITA, BITB, CMPA,
CMPB, EORA, EORB,
LDAA, LDAB, ORAA,
ORAB, SBCA, SBCB,
SUBA, SUBB
STAA, STAB
Cycles Cycle
#
1
2
Address Bus
R/W
Line
1
1
Data Bus
3
3
Opcode Address
Opcode Address + 1
Operand Address
1
Opcode
Operand Address (Low Byte)
(High Byte Assumed to be $00)
Operand Data
4-2
3
1
2
3
Opcode Address
Opcode Address + 1
Operand Address
1
1
0
Opcode
Operand Address (Low Byte)
(High Byte Assumed to be $00)
Data from Accumulator
*The reference number is given to provide a cross-refrerence to Table 10-1.
Table 10-2 Cycle-by-Cycle Operation — Inherent Mode (Sheet 4 of 4)
Reference
Number*
Address Mode
and Instructions
Cycles Cycle
#
Address Bus
R/W
Line
Data Bus
* The reference number is given to provide a cross-reference to Table 10-1.
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