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參數(shù)資料
| 型號： | MC68HC705F8FU |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 1.8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數(shù)： | 98/126頁 |
| 文件大?。?/td> | 736K |
| 代理商： | MC68HC705F8FU |
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MC68HC05F8
MOTOROLA
8-3
MANCHESTER ENCODER/DECODER
8
8.2.1.1
Idle State of Encoder
Upon reset the encoder enable bit (NCE) is cleared, ENCOOUT pin is at high impedance, internal
encoding clock is inhibited, and the encoder is in the idle state. The encode data register empty
ag (NCM) and the encoding completion ag (NCC) in the status register are both set.
8.2.1.2
Initialization of Encoder
The encoder is initialized by conguring the bit rate control bits (BR0, BS1) and setting NCE=1 to
place the encoder in the standby state. The encoding process is initiated by writing to the Encoder
Data register, which is then transferred to the encode data shift register ready for encoding. After
2 delay bits (ENCOOUT pin is low) and 2 sync bits, the encoded data is shifted out to the
ENCOOUT pin, LSB rst. See Figure 8-3 for a graphical representation.
8.2.1.3
Encode Data Register Empty Flag (NCM)
and Encode Interrupt
After the last data bit in the encode data shift register is encoded and output to ENCOOUT, a
trailing bit followed by two pause bits are generated to conclude a one byte transmission. After
this, if the Encode Data register is not empty, the encoding process is repeated.
When data from the encode data register is transferred to the encode data shift register, the
encoder data register empty ag (NCM) is set, causing an interrupt to be generated if the encode
interrupt is enabled (i.e. NIE = 1). The next byte of data to be encoded can be written in to the
encoder data register in an interrupt service routine. The NCM bit is automatically cleared by
writing to the encode data register after accessing the MANCD Status register.
8.2.1.4
End Pattern Generation and Next Data Byte Encoding
The end pattern of one byte sequence is generated automatically after the last bit. This pattern
consists of a trailing bit and two pause bits. After this, if the Encode Data register is empty,
ENCOOUT is set to high impedance, and the encoder returns to the standby state. The encoding
complete ag (NCC) will be set, and an interrupt is generated if the encoding complete interrupt
enable bit (CIE) is set. If the encode data register is not empty, the next encoding is started.
8.2.1.5
Disable Encoder
The encoder is disabled by setting NCE=0; causing the ENCOOUT pin to be tri-stated. If the NCE
bit is cleared while an encoding is in progress (indicated by NCC=0), the encoder will complete
encoding of the current byte, plus the end patterns, before going into idle.
TPG
71
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MC68HC705G1B | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| MC68HC705J1ACP | 功能描述:IC MCU 4MHZ 1.2K OTP 20-DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標(biāo)準(zhǔn)包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲器容量:64KB（64K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱:497-9032STM32F101T8U6-ND |
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