參數(shù)資料
型號： MC68HC705F8FU
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 1.8 MHz, MICROCONTROLLER, PQFP64
封裝： QFP-64
文件頁數(shù)： 101/126頁
文件大小： 736K
代理商： MC68HC705F8FU
MOTOROLA
8-6
MC68HC05F8
MANCHESTER ENCODER/DECODER
8
8.2.2.2
Data Bit Format Error Detection
During decoding, a bit format error detection is performed. If 00 or 11 appears at a time interval in
which one bit of data is expected, which means that bit format error occurs, then the decoder is
reset and returns to the start state.
8.2.2.3
Bit Rate Error Detection
During decoding, the input data is sampled by an internal clock, of which the frequency is 8 times
of the selected bit rate. If the bit rate of the input data varies exceeding 10% with reference to the
nominal value (see bit rate selection table), a bit rate error occurs and the data which is being
received is discarded. In this case the decoder is initialized and returns to the start state.
8.3
Manchester Encoder/Decoder Registers
8.3.1
MANCD Control Register
NCE - Encoder Enable Bit
1 (set)
–
Enable the encoder. A transition from 0 to 1 of this bit initiates
transmission sequence of one byte data, including 2 proceeding idle
bits and 2 ending pause bits.
0 (clear) –
Disable the encoder. When this bit is cleared, the encoder (except
the control bits) is reset and put in idle state.
If the NCE bit is cleared while an encoding is in progress (indicated by NCC=0), the encoder will
complete encoding of the current byte, plus the end patterns, before going idle. Clearing and
setting the NCE bit during encoding of a byte has no effect on the encoder operation. Normally,
after the last byte of data is written to the Encode Data register, the NCM bit will generate an
interrupt (if NIE=1), indicating that data have been transferred to the encode data shift register.
The user should then clear the NCE bit to put the encoder in the idle state.
NIE - Encoder Interrupt Enable Bit
1 (set)
–
Enable the encoder interrupt. If this bit is set, interrupt is generated
when the NCM ag is set.
0 (clear) –
Disable the encoder interrupt.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$2B
NCE
NIE
CIE
DCE
DIE
BR1
BR0
0000 0-00
TPG
74
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參數(shù)描述
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