參數(shù)資料
型號: MC68HC705F8FU
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 1.8 MHz, MICROCONTROLLER, PQFP64
封裝: QFP-64
文件頁數(shù): 90/126頁
文件大?。?/td> 736K
代理商: MC68HC705F8FU
MOTOROLA
7-2
MC68HC05F8
SERIAL PERIPHERAL INTERFACE
7
7.2.1
Serial Clock (SCK)
The state of SCK between transmissions must be logic “1”. The rst falling edge of SCK signals
the beginning of a transmission. At this time the MSB bit of received data is accepted at the
SDI pin and the MSB bit of transmitted data is presented at the SDO pin. Data is captured at the
SDI pin on the rising edge of SCK. Subsequent falling edges shift the data, and accept the next
received data bit at SDI pin, and present the next transmitted data bit at SDO pin. The transmission
is ended upon the receipt of the LSB bit.
In Master Mode, the format is identical except that the SCK pin is an output and the shift clock now
originates internally. The Master Mode transmission frequency is xed at E/4.
Care should be taken when enabling the SPI; additional clock edges may be present when the
port is switched from standard I/O to SPI.
Figure 7-1 SPI Master-Slave Interconnection
Figure 7-2 SPI Port Timing
8-BIT SHIFT REGISTER
SPI
MASTER
SLAVE
SDO
SDI
SCK
8-BIT SHIFT REGISTER
CLOCK GENERATOR
(447.5KHz)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
112ns 112ns
SCK
SDO
SDI
TPG
64
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相關代理商/技術參數(shù)
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