參數(shù)資料
型號: MC68HC705F8FU
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 1.8 MHz, MICROCONTROLLER, PQFP64
封裝: QFP-64
文件頁數(shù): 100/126頁
文件大?。?/td> 736K
代理商: MC68HC705F8FU
MC68HC05F8
MOTOROLA
8-5
MANCHESTER ENCODER/DECODER
8
8.2.2
Decoder
The Manchester decoder is used to convert incoming Manchester codes on the DECOIN pin to
NRZ data format for processing.
Upon reset the decoder is disabled, decoder enable bit DCE=0. To initiate the decoding process,
the bit rate is rst congured. Setting DCE activates the internal decoding clock, the decoder
enters the start state and the DECOIN pin begins to be sampled. After a low state is conrmed,
the receiver starts to hunt for the 2 bits SYNC pattern. if it is detected, the decoding procedure
starts, the decode logic converts the data bits from Manchester code format to NRZ format and
shifts the result to the decode shift register bit by bit. After all 8 bits have been received and
converted to one data byte, the end pattern of a trailing bit plus two bit pause is veried. If the
pattern followed is correct, the decode ag is set and an interrupt is generated, otherwise the
decoder is reset and returns to the start state.
8.2.2.1
Decoder Overrun
After one byte of data is received and end pattern veried, the decode output ag (DCF) is
checked rst, if it is zero (indicating the Decode Register is empty), one byte of data which has
been received is loaded to the Decode Register and interrupt is generated with the decode output
ag set (DCF=1), otherwise the receive overrun ag is set and an interrupt is generated.
Figure 8-3 Encoder Timing Diagram
A sequence of one byte data
8 bits data
12345678
ENCOOUT
D0
D1
D2
D3
D4
D5
D6
D7
00111010
High Z
1st
SYN bit
2nd
SYN bit
2 bits SYNC
2 bits
DELAY
2 bits
PAUSE
t
≤1 bit time
NCE (encode enable)
Trailing
bit
ENCODER OUT
TPG
73
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