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參數(shù)資料
| 型號： | MC68HC705F8FU |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 1.8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數(shù)： | 69/126頁 |
| 文件大?。?/td> | 736K |
| 代理商： | MC68HC705F8FU |
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MC68HC05F8
MOTOROLA
5-11
INTERRUPTS
5
5.8
Manchester Coder (MANCD) Interrupt
A Manchester Coder interrupt occurs when one of the interrupt ags in the MANCD Status register
(location $2C) is set, provided the interrupt mask bit in the Condition Code register is cleared and
the enable bit in the MANCD Control register ($2B) is enabled. When the interrupt is recognized,
the current state of the CPU is pushed onto the stack and the interrupt mask bit in the condition
code register is set. This masks any further interrupt until the present one is serviced. The MANCD
interrupt causes the program counter to vector to memory location $FFF2 and $FFF3 which
contains the starting address of the interrupt’s service routine.
Software in the MANCD interrupt service routine must determine the priority and the cause of the
MANCD interrupt by examining the interrupt ags located in the MANCD Status register.
There are four interrupt ags associated with MANCD interrupts:
NCM - Encoder Data Register Empty Flag
1 (set)
–
Encoder Data register is empty.
0 (clear) –
Encoder Data register is not empty.
This bit is cleared by accessing the MANCD Status register (with NCM set), followed by writing to
the Encoder Data register.
NCC - Encoding Completion Flag
1 (set)
–
Encoder is disabled (NCE=0) or, NCE=1 and transmission of the
data in the shift register is completed.
0 (clear) –
Transmission of data in process.
This bit is cleared by writing to the Encoder Data register when NCE bit is set.
DCF - Decoder Data Register Full Flag
1 (set)
–
One byte of data received with end pattern veried.
0 (clear) –
Decoder Data register not full.
This bit is cleared when the MANCD Status register is accessed (with DCF set) followed by a read
of the Decoder Data register, or by clearing the DCE bit.
OVF - Overrun Flag
1 (set)
–
An overrun has occurred.
0 (clear) –
An overrun has not occurred.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$2C
NCM
NCC
DCF
OVF
-
1100 ----
TPG
45
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