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參數(shù)資料
| 型號： | MC68HC705F8FU |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 1.8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數(shù)： | 76/126頁 |
| 文件大?。?/td> | 736K |
| 代理商： | MC68HC705F8FU |
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MC68HC05F8
MOTOROLA
6-5
TIMERS
6
corresponding input edge bit (IEDG). Reset does not affect the contents of the Input Capture
register.
The result obtained from an input capture will be one greater than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition. This delay is
required for internal synchronization. Resolution is zero or one count of the free-running counter,
which is 4xRTB internal bus clock cycles.
The free-running counter contents are transferred to the Input Capture register on each valid
signal transition whether the input capture ag (ICF) is set or clear. The Input Capture register
always contains the free-running counter value that corresponds to the most recent input
capture.After a read of the input capture register MSB ($1A), the counter transfer is inhibited until
the LSB ($1B) is also read. This characteristic causes the time used in the input capture software
routine and its interaction with the main program to determine the minimum pulse period. A read
of the input capture register LSB ($1B) does not inhibit the free-running counter transfer since they
occur on opposite edges of the internal bus clock.
6.1.4
Timer Control Register (TCR)
The TCR is a read/write register containing ve control bits. Three bits control interrupts
associated with the three ag bits found in the timer status register (discussed below). The other
two bits control: 1) which edge is signicant to the input capture edge detector (i.e., negative or
positive), and 2) the next value to be clocked to the Output Level registers in response to a
successful output compare. The Timer Control register and the free-running counter are the only
sections of the timer affected by reset. The TCMP pin is forced low during external reset and stays
low until a valid compare changes them to high. Denition of each bit is as follows:
ICIE - Input Capture Interrupt Enable
1 (set)
–
Input Capture interrupt enabled.
0 (clear) –
Input Capture interrupt disabled.
OCIE - Output Compare Interrupt Enable
1 (set)
–
Output Compare interrupt enabled.
0 (clear) –
Output Compare interrupt disabled.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on Reset
$18
ICIE
OCIE
TOIE
0
IEDG
OLVL
0000 00u0
TPG
51
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| MC68HC705J1ACP | 功能描述:IC MCU 4MHZ 1.2K OTP 20-DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標準包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲器容量:64KB（64K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱:497-9032STM32F101T8U6-ND |
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