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參數(shù)資料
| 型號： | MC68HC11G5CFN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 71/195頁 |
| 文件大?。?/td> | 982K |
| 代理商： | MC68HC11G5CFN |
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CPU, ADDRESSING MODES AND INSTRUCTION SET
12-12
The XIRQ interrupt mask (X) bit is another unusual case. The definition of this bit specifically states
that software shall not be allowed to change X from 0 to 1, in fact, this is even prohibited by hardware
logic. This immediately eliminates a need for a set X instruction. For arguments similar to those used
for the S bit, the TAP instruction is preferred over a clear X instruction as a means of clearing X
because TAP makes it a little less likely that X will become cleared before the programmer really
intended to clear it.
The half-carry (H) bit needs no set or clear instructions because this condition code bit is only used
by the DAA instruction to adjust the result of a BCD add or subtract. The H bit is not used as a test
condition for any branches so it would not be useful to be able to set or clear this bit.
This leaves only the negative (N) and zero (Z) condition code bits. In contrast to S, X, and H, it is
often useful to be able to easily set or clear these flag bits. A clear accumulator instruction such as
CLRB will clear both the N and Z condition code bits. The instruction “LDAA #$80” causes both N
and Z to be set. Since there are so many simple instructions that can accomplish setting or clearing
of N and Z, it is not necessary to provide specific set and clear instructions for N and Z in this group.
12.3.4
Program Control Instructions
This group of instructions is used to control the flow of a program rather than to manipulate data.
Since this group is so large it has been further divided into five subgroups:
1. Branches,
2. Jumps,
3. Subroutine calls and returns,
4. Interrupt handling,
5. Miscellaneous.
12.3.4.1
Branches
These instructions allow the CPU to make decisions based on the contents of the condition code
bits. All decision blocks in a flow chart would correspond to one of the conditional branch instructions
which are summarized in the following table.
Freescale
Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc.
..
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MC68HC11G5,
MC68HC11G7,
MC68HC711G5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC11G5CFN | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC84 |
| MC68HC11L6VFU23 | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQFP64 |
| MC68HC11L6CFU22 | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64 |
| MC68HC11L6VFU22 | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64 |
| MC68HC11L6MFU22 | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC11G7 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller Unit |
| MC68HC11G7CFN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| MC68HC11K0 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
| MC68HC11K0CFN2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:8-Bit Microcontroller |
| MC68HC11K0CFN3 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:8-Bit Microcontroller |
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