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參數(shù)資料
| 型號： | MC68HC11G5CFN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 129/195頁 |
| 文件大小： | 982K |
| 代理商： | MC68HC11G5CFN |
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INPUT/OUTPUT PORTS
4-1
SECTION 4
INPUT/OUTPUT PORTS
There are seven 8-bit I/O ports, one 6-bit I/O port and one 4-bit I/O port on the MC68HC11G5. Most
of the 66 I/O pins serve multiple purposes depending on the configuration of the MCU system
(see Table 2-3). The configuration is controlled in turn, by hardware mode selection as well as by
several internal control registers.
Ports A, C, D, G, H, and J may be used as general purpose input and/or output pins as specified
by DDRA, DDRC, DDRD, DDRG, DDRH, and DDRJ. Ports B, E, and F have fixed data direction and
thus do not require DDR control registers.
Port signals can always be sensed (read) even if they are configured as general purpose outputs
or are dedicated to on-chip peripheral functions. Reading the port address returns the sensed logic
level at the pin when the pin is configured as an input, and the logic sense at the input to the pin driver
is sensed when the pin is configured as an output.
I/O pins default to being general purpose I/O lines unless an internal function which uses that pin
is specifically enabled. When a pin is dedicated to an internal peripheral function the associated
DDR bit in some cases still controls whether the line is an input or an output. The SPI, timer input
captures and pulse accumulator follow this rule.
Several functions override the state of the DDRs. The SCI forces the I/O state of the two associated
Port D lines. The timer also forces the I/O state of each associated Port A line when an output
compare using a Port A or Port J line is enabled. Both the PWM timer and the event counter
also override the associated DDR bits. In these cases the data direction bits will have no effect on
these lines.
When a pin is dedicated to an on-chip peripheral function, writes to the associated PORTx bit do
not affect the pin but are stored in an internal latch such that, if the pin becomes available for general
purpose output, the driven level will be the last value written to the PORTx bit.
4.1
MODE DEPENDENCIES
The MCU mode is controlled by two mode select bits (SMOD and MDA) in the HPRIO register which
are in turn controlled by the two mode select pins (MODA and MODB).
In the expanded modes (normal expanded and test), ports B, C, E and F, R/W, and LIR are dedicated
to address, data, and control signals and may not be used for alternate I/O functions. In order to
Freescale
Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc.
..
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MC68HC11G5,
MC68HC11G7,
MC68HC711G5
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| MC68HC11G7 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller Unit |
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