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參數(shù)資料
| 型號(hào)： | MC68HC11G5CFN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 40/195頁 |
| 文件大?。?/td> | 982K |
| 代理商： | MC68HC11G5CFN |
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EVENT COUNTER
11-4
The two counter registers (EVCNT1 and EVCNT2) are clocked by the same signal via the INPUT1
selector. This clock signal can be the E-clock, a scaled E-clock or an external signal applied to the
EVI1 pin. If the clock signal is the E-clock or a derivative, an external gating signal can be applied
to EVI1. If EVI1 is not used for clock or gate, it can be used as a normal I/O pin (PH5).
The 8-bit phase shift value (X) is stored in ECMP2A (in the PA unit). When the count in EVCNT2
reaches this value, the successful compare causes a clearing signal to be applied to EVCNT1 in the
PWM unit and starts the PWM sequence.
The value of the output pulse width (Y) is stored in ECMP1A, however the start time and the duration
of this pulse can be modified by a skew value (X’) which is stored in ECMP1B. If no skew is included,
i.e. ECMP1B is set to zero, then a compare occurs when EVCNT1 is cleared, and the output signal
changes state immediately after the initial phase shift period X introduced by the PA unit. The effect
of storing a skew value (X’) in ECMP1B is to delay the leading edge of the PWM output pulse by the
phase shift plus the skew value (X+X’).
The trailing edge of the output pulse is generated when there is a match between EVCNT1 and
ECMP1A (X + Y). Note that the skew value does not affect the timing of the trailing edge of the output
pulse, but only the leading edge. Consequently the output pulse width is reduced by the skew value
from Y to Y-X’. A maskable interrupt signal EVENT1 is generated when there is a match between
EVCNT1 and ECMP1A.
A clearing signal on the EVI2 pin clears EVCNT2 in the PA unit and restarts the sequence.
ECMP2B can be used to generate an interrupt signal, EVENT2, when EVCNT2 accumulates a
desired number of clock pulses.
11.2.2
Register Functions in Mode 0
11.2.2.1
Counter 1 (EVCNT1)
This counter drives the PWM section of the event counter. It is cleared by a successful comparison
between ECMP2A and EVCNT2. The source chosen by input selector INPUT1 is used as the clock
input to both counters (EVCNT1 and EVCNT2). The width and time of the output pulse is determined
by the value in this counter matching the values in ECMP1A and ECMP1B.
11.2.2.2
Compare Register 1A (ECMP1A); (Y)
This compare register holds the nominal value of the output pulse width. Note that the actual output
pulse width value will be equal to the value contained in ECMP1A minus the skew value which is
held in event compare register 1B (ECMP1B). An interrupt signal, EVENT1 is generated when there
is a match between ECMP1A and EVCNT1.
11.2.2.3
Compare Register 1B (ECMP1B); (X’)
This compare register holds a value which adjusts the phase skew between the external signal (on
EVI2) and the leading edge of the desired output signal. If the value in this register is zero, then the
actual pulse width depends only on the value Y in ECMP1A. If the value in this register is equal to
Freescale
Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc.
..
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MC68HC11G5,
MC68HC11G7,
MC68HC711G5
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