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參數(shù)資料
| 型號(hào)： | MC68HC08LT8 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | Microcontrollers |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 79/156頁(yè) |
| 文件大?。?/td> | 1030K |
| 代理商： | MC68HC08LT8 |
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Functional Description
MC68HC08LT8 Data Sheet, Rev. 1
Freescale Semiconductor
79
8.4.2 LCD Voltages (V
LCD,
V
LCD1,
V
LCD2
, V
LCD3
)
The voltage V
LCD
is from the V
LCD
pin and must not exceed V
DD
. V
LCD1
, V
LCD2
, and V
LCD3
are internal
bias voltages for the LCD driver waveforms. They are derived from V
LCD
using a resistor ladder (see
Figure 8-3
).
The relative potential of the LCD voltages are:
V
LCD
= V
DD
V
LCD1
= 2/3
×
(V
LCD
– V
bias
)
V
LCD2
= 1/3
×
(V
LCD
– V
bias
)
V
LCD3
= V
bias
The V
LCD3
bias voltage, V
bias
, is controlled by the LCD contrast control bits, LCCON[2:0].
8.4.3 LCD Cycle Frame
The LCD driver module uses the 32KXCLK (see
Chapter 5 Oscillator (OSC)
) as the input reference clock.
This clock is divided to produce the LCD waveform base clock, LCDCLK, by configuring the LCLK[2:0]
bits in the LCD clock register. The LCDCLK clocks the backplane and the frontplane output waveforms.
The LCD cycle frame is determined by the equation:
For example, for 1/3 duty and 256Hz waveform base clock:
8.4.4 Fast Charge and Low Current
The default value for each of the bias resistors (see
Figure 8-3
), R
LCD
, in the resistor ladder is
approximately 37k
at V
LCD
= 3V. The relatively high current drain through the 37k
resistor ladder may
not be suitable for some LCD panel connections. Lowering this current is possible by setting the LC bit in
the LCD control register, switching the R
LCD
value to 146k
.
Although the lower current drain is desirable, but in some LCD panel connections, the higher current is
required to drive the capacitive load of the LCD panel. In most cases, the higher current is only required
when the LCD waveforms change state (the rising and falling edges in the LCD output waveforms). The
fast charge option is designed to have the high current for the switching and the low current for the steady
state. Setting the FC bit in the LCD control register selects the fast charge option. The R
LCD
value is set
to 37k
(for high current) for a fraction of time for each LCD waveform switching edge, and then back to
146k
for the steady state period. The duration of the fast charge time is set by configuring the
FCCTL[1:0] bits in the LCD clock register, and can be LCDCLK/32, LCDCLK/64, or LCDCLK/128.
Figure
8-4
shows the fast charge clock relative to the BP0 waveform.
LCD CYCLE FRAME =
LCD WAVEFORM BASE CLOCK
×
DUTY
1
LCD CYCLE FRAME =
256
×
(1/3)
1
= 11.72 ms
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