參數(shù)資料
型號： MC68HC08LT8
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： Microcontrollers
中文描述： 微控制器
文件頁數(shù)： 131/156頁
文件大?。?/td> 1030K
代理商： MC68HC08LT8
Instruction Set Summary
MC68HC08LT8 Data Sheet, Rev. 1
Freescale Semiconductor
131
BHS
rel
Branch if Higher or Same
(Same as BCC)
Branch if IRQ Pin High
Branch if IRQ Pin Low
PC
←
(PC) + 2 +
rel
(C) = 0
– – – – – – REL
24
rr
3
BIH
rel
BIL
rel
BIT #
opr
BIT
opr
BIT
opr
BIT
opr
,X
BIT
opr
,X
BIT ,X
BIT
opr
,SP
BIT
opr
,SP
PC
←
(PC) + 2 +
rel
IRQ = 1
PC
←
(PC) + 2 +
rel
IRQ = 0
– – – – – – REL
– – – – – – REL
2F
2E
A5
B5
C5
D5
E5
F5
9EE5
9ED5
rr
rr
ii
dd
hh ll
ee ff
ff
3
3
2
3
4
4
3
2
4
5
Bit Test
(A) & (M)
0 – –
–
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
ff
ee ff
BLE
opr
Branch if Less Than or Equal To
(Signed Operands)
Branch if Lower (Same as BCS)
Branch if Lower or Same
Branch if Less Than (Signed Operands)
Branch if Interrupt Mask Clear
Branch if Minus
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
Branch Always
PC
←
(PC) + 2 +
rel
(Z)
| (N
⊕
V
) =
1 – – – – – – REL
93
rr
3
BLO
rel
BLS
rel
BLT
opr
BMC
rel
BMI
rel
BMS
rel
BNE
rel
BPL
rel
BRA
rel
PC
←
(PC) + 2 +
rel
(C) = 1
PC
←
(PC) + 2 +
rel
(C) | (Z) = 1
PC
←
(PC) + 2 +
rel
(N
⊕
V
) =
1
PC
←
(PC) + 2 +
rel
(I) = 0
PC
←
(PC) + 2 +
rel
(N) = 1
PC
←
(PC) + 2 +
rel
(I) = 1
PC
←
(PC) + 2 +
rel
(Z) = 0
PC
←
(PC) + 2 +
rel
(N) = 0
PC
←
(PC) + 2 +
rel
– – – – – – REL
– – – – – – REL
– – – – – – REL
– – – – – – REL
– – – – – – REL
– – – – – – REL
– – – – – – REL
– – – – – – REL
– – – – – – REL
25
23
91
2C
2B
2D
26
2A
20
01
03
05
07
09
0B
0D
0F
21
00
02
04
06
08
0A
0C
0E
10
12
14
16
18
1A
1C
1E
rr
rr
rr
rr
rr
rr
rr
rr
rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd
dd
dd
dd
dd
dd
dd
dd
3
3
3
3
3
3
3
3
3
5
5
5
5
5
5
5
5
3
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
BRCLR
n
,
opr
,
rel
Branch if Bit
n
in M Clear
PC
←
(PC) + 3 +
rel
(Mn) = 0
– – – – –
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
BRN
rel
Branch Never
PC
←
(PC) + 2
– – – – – – REL
BRSET
n
,
opr
,
rel
Branch if Bit
n
in M Set
PC
←
(PC) + 3 +
rel
(Mn) = 1
– – – – –
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
BSET
n
,
opr
Set Bit
n
in M
Mn
←
1
– – – – – –
BSR
rel
Branch to Subroutine
PC
←
(PC) + 2; push (PCL)
SP
←
(SP) – 1; push (PCH)
SP
←
(SP) – 1
PC
←
(PC) +
rel
PC
←
(PC) + 3 + rel (A) – (M) = $00
PC
←
(PC) + 3 + rel (A) – (M) = $00
PC
←
(PC) + 3 + rel (X) – (M) = $00
PC
←
(PC) + 3 + rel (A) – (M) = $00
PC
←
(PC) + 2 + rel (A) – (M) = $00
PC
←
(PC) + 4 + rel (A) – (M) = $00
C
←
0
I
←
0
– – – – – – REL
AD
rr
4
CBEQ
opr,rel
CBEQA #
opr,rel
CBEQX #
opr,rel
CBEQ
opr,
X+
,rel
CBEQ
X+
,rel
CBEQ
opr,
SP
,rel
CLC
CLI
Compare and Branch if Equal
– – – – – –
DIR
IMM
IMM
IX1+
IX+
SP1
31
41
51
61
71
9E61
98
9A
dd rr
ii rr
ii rr
ff rr
rr
ff rr
5
4
4
5
4
6
1
2
Clear Carry Bit
Clear Interrupt Mask
– – – – – 0 INH
– – 0 – – – INH
Table 14-1. Instruction Set Summary (Sheet 2 of 6)
Source
Form
Operation
Description
Effect
on CCR
A
M
O
O
C
V H I N Z C
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