參數(shù)資料
型號: MC68HC08LT8
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Microcontrollers
中文描述: 微控制器
文件頁數(shù): 104/156頁
文件大?。?/td> 1030K
代理商: MC68HC08LT8
Input/Output (I/O) Ports
MC68HC08LT8 Data Sheet, Rev. 1
104
Freescale Semiconductor
9.6 Port E
Port E is an 8-bit special function port that shares all of its port pins with the liquid crystal display (LCD)
driver module.
9.6.1 Port E Data Register (PTE)
The port E data register contains a data latch for each of the eight port E pins.
PTE[7:0] — Port E Data Bits
These read/write bits are software programmable. Data direction of each port E pin is under the control
of the corresponding bit in data direction register E. Reset has no effect on port E data.
FP[10:3] — LCD Driver Frontplanes 10–3
FP[10:3] are pins used for the frontplane output of the LCD driver module. The enable bit, PEE, in the
CONFIG2 register and LCDE bit in the LCDCR register, determines whether the
PTE7/FP10–PTE0/FP3 pins are LCD frontplane driver pins or general-purpose I/O pins.
See
Chapter 8 Liquid Crystal Display (LCD) Driver
.
9.6.2 Data Direction Register E (DDRE)
Data direction register E determines whether each port E pin is an input or an output. Writing a logic 1 to
a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the output buffer.
DDRE[7:0] — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears DDRE[7:0], configuring all port E pins
as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 9-14
shows the
port E I/O logic.
Address:
$0009
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PTE7
PTE6
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0
Write:
Reset:
Unaffected by reset
Alternative Function:
FP10
FP9
FP8
FP7
FP6
FP5
FP4
FP3
Figure 9-15. Port E Data Register (PTE)
Address:
$0008
Bit 7
6
5
4
3
2
1
Bit 0
Read:
DDRE7
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
DDRE1
DDRE0
Write:
Reset:
0
0
0
0
0
0
0
0
Figure 9-16. Data Direction Register E (DDRE)
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